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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66661完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
| dc.contributor.author | Chia-Chi Ho | en |
| dc.contributor.author | 何家齊 | zh_TW |
| dc.date.accessioned | 2021-06-17T00:49:36Z | - |
| dc.date.available | 2013-01-17 | |
| dc.date.copyright | 2012-01-17 | |
| dc.date.issued | 2011 | |
| dc.date.submitted | 2011-11-30 | |
| dc.identifier.citation | [1] A. A. Abidi, “The Path to the Software-Defined Radio Receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 5, pp. 954-966, May, 2007.
[2] H. van der Ploeg and B. Nauta, Calibration Techniques in Nyquist A/D Converters, Springer, Dordrecht, 2006. [3] B. Murmann and B. E. Boser, “A 12-bit 75MS/s Pipelined ADC Using Open-Loop Residue Amplification,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dec. 2003. [4] B. Ginetti, P. G. A. Jespers, and A. Vandemeulebroecke, “A CMOS 13-b Cyclic RSD A/D Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 957-965, Jul. 1992. [5] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s Analog-to-Digital Converter,” IEEE J. of Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. [6] M. Gustavsson, J. J. Wikner, and N. Tan, CMOS Data Converters for Communications,Kluwer Academic Publisher, Boston, 2000. [7] S. H. Lewis, 'Optimizing the Stage Resolution in Pipelined, Multistage, Analog-to-Digital Converters for Video-Rate Applications,' IEEE Trans. Circuits Syst II, vol. 39, pp. 515–523, Aug. 1992. [8] P. C. Yu and H.-S. Lee, “A 2.5-V 12-b 5-MSample/s Pipelined CMOS ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 12, pp. 1854-1861, Dec. 1996. [9] K. Nagaraj, H. S. Fetterman, J. Anidjar, S. H. Lewis, and R. G. Renninger, “A 250mW 8b 52Msample/s Parallel-Pipelined A/D Converter with Reduced Number of Amplifiers,” IEEE J. Solid-State Circuits, vol. 32, no. 3, pp. 312-320, Mar. 1997. [10] M.-J. Kim, H.-S. Yoon, Y.-J. Lee, and S.-H. Lee, “An 11b 70 MHz 1.2 mm2 49 mW 0.18 um CMOS ADC with On-Chip Current/Voltage References,” in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2002, pp. 463-466. [11] J. Doernberg, H.-S. Lee, and D. A. Hodges, “Full-Speed Testing of A/D Converters,” IEEE J. Solid-State Circuits, vol. SC-19, pp. 820-827, Dec. 1984. [12] B.-G. Lee and Robin M. Tsang, “A 10-bit 50 MS/s Pipelined ADC with Capacitor-Sharing and Variable-gm Opamp,” IEEE J. Solid-State Circuits, vol. 44, pp 883-890, Mar. 2009. [13] G. Geelen, E. Paulus, D. Simanjuntak, H. Pastoor, and R. Verlinden, “A 90nm CMOS 1.2V 10b Power and Speed Programmable Pipelined ADC with 0.5pJ/Conversion-Step,” ISSCC Dig. Tech. Papers, pp. 782-791, Feb. 2006. [14] Z. Cao, S. Yan, and Y. Li, “A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 862-873, Mar. 2009. [15] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, Apr. 2010. [16] Y. Zhu, C. H. Chan, U. F. Chio, S. W. Sin, S. P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, no. 6, pp. 1111-1121, June 2010. [17] J. Yang, T. L. Naing, and R. W. Brodersen, “A 1 GS/s 6 Bit 6.7 mW successive approximation ADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469-1478, Aug. 2010. [18] F. Kuttner, “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2002, pp. 176-177. [19] J. Craninckx and G. Van der Plas, “A 65 fJ/conversion-step 0-to-50 MS/s 0-to-0.7 mW 9 b charge-sharing SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247. [20] V. Giannini, P. Nuzzo, V. Chironi, A. Baschirotto, G. Van der Plas, and J. Craninckx, “An 820 μW 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 238–239. [21] L. Brooks and H.-S. Lee, “A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC,” IEEE J. of Solid-State Circuits, Vol. 42, pp. 2677-2687, Dec., 2007. [22] L. Brooks and H.-S. Lee, “A 12b 50MS/s Fully Differential Zero-Crossing-Based ADC Without CMFB,” in ISSCC Dig. Tech. Papers, Feb., 2009, pp. 166-167. [23] J. Hu, N. Dolev and B. Murmann, “A 9.4-bit, 50-MS/s, 1.44-mW Pipelined ADC Using Dynamic Source Follower Residue Amplification,” IEEE J. of Solid-State Circuits, Vol. 44, pp. 1057-1066, Apr., 2009. [24] I. Ahmed, J. Mulder and D. A. Johns, “A 50MS/s 9.9mW Pipelined ADC with 58dB SNDR in 0.18um CMOS Using Capacitive Charge-Pumps,” in ISSCC. Dig. Tech. Papers, Feb., 2009, pp. 164-165. [25] Y. Fujimoto, H. Tani, M. Maruyama, H. Akada, H. Ogawa, and M. Miyamoto, “A low-power switched-capacitor variable gain amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1213-1216, July 2004. [26] H.-H. Nguyen, H.-N. Nguyen, J.-S. Lee, and S.-G. Lee, 'A binary-weighted switching and reconfiguration-based programmable gain amplifier,' IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 9, pp. 699–703, Sep. 2009. [27] I.-H. Wang and S.-I. Liu, “A 0.18-μm CMOS 1.25-Gbps automatic-gaincontrol amplifier,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 55, no. 2, pp. 136–140, Feb. 2008. [28] J. P. Alegre, S. Celma, B. Calvo, N. Fiebig, and S. Halder, “SiGe analog AGC circuit for an 802.11a WLAN direct conversion receiver,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 93–96, Feb. 2009. [29] P. Hazucha, T. Karnik, B. Bloechel, C. Parsons, D. Finan, and S. Borkar, 'An area-efficient, integrated, linear regulator with ultra-fast load regulation,' Symp. VLSI Circuits Dig. 18, pp. 218 - 221, June 2004. [30] E. Alpman, H. Lakdawala, L. R. Carley, and K. Soumyanath, 'A 1.1V 50mW 2.5GS/s 7b time-interleaved C-2C SAR ADC in 45nm LP digital CMOS,' ISSCC Dig. Tech. Papers, pp. 76-77, 77a, Feb. 2009. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66661 | - |
| dc.description.abstract | 近年來，隨著無線通訊應用的快速成長，不同的無線通訊規格也相繼出現，便需要不同的收發機，因此，如何整合這些通訊系統在同一收發機內成為一個熱門的議題。軟體無線電(Software-Defined Radio，SDR)技術[1]即是指在目前各種不同的無線通訊規格中，藉由在不同信號調變方式之間建立互通性，共用相同類比射頻的前端電路，最後再由軟體進行信號解調以及處理。如此就能使用單一收發機，同時進行多規格之通訊。然而，欲完成此種軟體無線電收發機，便不可或缺一個具有不同解析度及轉換頻率的多規格類比數位轉換器。
管線式類比數位轉換器已被廣泛使用於中解析度且高速的應用中。本論文中提出改良電容切換運算及可調整運算放大器，使管線式類比數位轉換器在不同規格的需求下達到更有效率的功率耗損。所設計的類比數位轉換器，其數位碼輸出的訊雜比可達48.6 dB。本管線式類比數位轉換器採用九十奈米CMOS製程製作，其中核心面積為0.27平方毫米。利用運算放大器與電容共享的技巧，在一伏供應電壓、兩億赫茲轉換速率下，可將核心消耗的功率降低至32毫瓦，再加上運算放大器的調變，於一億赫茲與五千萬赫茲的轉換速率下可分別將功率再降至18.5及13毫瓦。最後，在本論文末，針對管線式架構與近來快速發展的連續漸進式類比數位轉換器進行分析，以引導未來的發展方向。 | zh_TW |
| dc.description.abstract | In recent years, applications of wireless communication have been growing rapidly. Meanwhile, more specifications of wireless communication have been developed, so different receivers are needed. Therefore, it is desirable to combine these systems into one receiver. Software-Defined Radio, SDR [1], is one of these techniques to realize a multi-standard receiver by processing signal in the software. By this method, resources such as analog RF frontends and analog-to-digital converters (ADCs) can be shared between different modulations. To do so, an ADC that is able to adjust its resolution and conversion rate is necessary.
The pipelined ADC has been widely utilized in mid-resolution, high-speed applications. In this thesis, a switched-capacitor technique and a power reconfigurable opamp are proposed, which allow the system to optimize its power consumption with system bandwidth and resolution. Output codes of the designed ADC exhibit a SNDR of 48.6 dB. Fabricated in the 90nm CMOS technology, the core of the reconfigurable pipelined ADC occupies 0.27mm2. The opamp-sharing and capacitor-sharing techniques reduce the core power consumption to 32mW from a 1V supply voltage at 200MS/s. By the reconfiguration, the power consumption can be reduced to 18.5mW and 13mW at the conversion rate of 100MS/s and 50MS/s, respectively. At the end of this thesis, an analysis is performed to compare pipelined architectures with fast-growing SAR ADCs. This analysis helps the direction of future development. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T00:49:36Z (GMT). No. of bitstreams: 1 ntu-100-R97943111-1.pdf: 5067677 bytes, checksum: 8ddb0058ed3c4baccd2ac4066c6be42a (MD5) Previous issue date: 2011 | en |
| dc.description.tableofcontents | 口試委員審定書(中/英)
誌謝 i 摘要 iii Abstract iv Contents v List of Figures ix List of Tables xiii Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of Pipelined A/D Converters 5 2.1 Introduction 5 2.2 General View of Pipelined ADC 5 2.3 Digital Correction 7 2.3.1 Out of Range Error 8 2.3.2 Over Range Error Correction 9 2.3.3 1.5-Bit Pipelined Stage 12 2.3.4 Error Correction Extension 14 2.4 Pipelined Latency 14 2.5 Summary 15 Chapter 3 A Reconfigurable Pipelined A/D Converter with Half Load 17 3.1 Introduction 17 3.2 A Reconfigurable Operational Amplifier 18 3.3 Half-Load Architecture 24 3.4 Circuit Details 26 3.4.1 Flip-Around Sample-and-Hold Amplifier 26 3.4.2 Pipelined Stage with Closed-Loop Amplifier 29 3.4.3 Bias Circuit 32 3.4.4 Clock Generator 33 3.5 Summary 35 Chapter 4 Experimental Results 37 4.1 Introduction 37 4.2 Post-Layout Simulations 37 4.3 Print Circuit Board Design 39 4.4 Measurement Setup 42 4.5 Measurement Results 44 4.6 Summary 47 Chapter 5 Analysis of Pipelined and SAR A/D Converters with Peripheral Circuitry 49 5.1 Introduction 49 5.2 General View of SAR ADC 51 5.3 Simulation Model 54 5.3.1 Size of Sampling Capacitor 55 5.3.2 Power Dissipation of MDAC Opamp 60 5.3.3 Power Dissipation of Reference Buffer 65 5.3.4 Power Dissipation of PGA 67 5.3.5 Other Modified Architectures of SAR ADC 68 5.4 Simulation Result 70 5.4.1 Size of Sampling Capacitor 70 5.4.2 Power Dissipation of Core and Driving Circuit 73 5.5 Spice Verification 76 5.6 Summary 77 Chapter 6 Conclusions and Future Works 79 6.1 Conclusions 79 6.2 Future Works 79 Bibliography 81 Biography 85 | |
| dc.language.iso | en | |
| dc.subject | 連續漸進式類比數位轉換器 | zh_TW |
| dc.subject | 可適性系統 | zh_TW |
| dc.subject | 無線通訊 | zh_TW |
| dc.subject | 軟體無線電 | zh_TW |
| dc.subject | 類比數位轉換 | zh_TW |
| dc.subject | 運算放大器共享技巧 | zh_TW |
| dc.subject | 管線式類比數位轉換器 | zh_TW |
| dc.subject | analog-to-digital conversion | en |
| dc.subject | SAR ADC | en |
| dc.subject | pipelined ADC | en |
| dc.subject | opamp-sharing technique | en |
| dc.subject | Software-Defined Radio | en |
| dc.subject | Wireless communication | en |
| dc.title | 應用放大器共享技巧之可重置式十位元兩億赫茲管線式類比數位轉換器 | zh_TW |
| dc.title | A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter with Opamp-Sharing Technique | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),陳巍仁(Wei-Zen Chen),劉深淵(Shen-Iuan Liu) | |
| dc.subject.keyword | 無線通訊,可適性系統,軟體無線電,類比數位轉換,運算放大器共享技巧,管線式類比數位轉換器,連續漸進式類比數位轉換器, | zh_TW |
| dc.subject.keyword | Wireless communication,Software-Defined Radio,analog-to-digital conversion,opamp-sharing technique,pipelined ADC,SAR ADC, | en |
| dc.relation.page | 86 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2011-12-01 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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