GPS訊號擷取程序之硬體架構及資源整合

Abstract

訊號擷取在GPS系統中為一個粗略的同步程序，其最重要的目的為搜尋天空中的可見衛星並且求出其粗略碼相位及都卜勒頻移等資訊。然而龐大的搜索空間造成擷取程序的高運算複雜度及硬體複雜度。另外，為了增進擷取程序對較微弱訊號的偵測敏感度，常會採用同調積分及非同調積分，這兩種運算皆須要額外的記憶體來儲存其運算結果，因而更加提高了擷取程序的硬體需求。為了降低擷取程序的硬體複雜度，本論文提出了兩種硬體資源整合架構可以確實的降低擷取程序之硬體需求。 典型的擷取程序中，碼相位搜尋需要兩種硬體資源來完成同調積分及交相關運算：用於執行同調積分的記憶體以及用於執行相關運算的位移暫存器。我們提出的硬體資源整合架構，其最主要的精神即是只使用其中一種硬體資源來完成同調積分及交相關這兩種運算，如此一來擷取程序的硬體複雜度可以確實的下降，且不犧牲偵測機率。 論文中除了對提出的硬體架構及其相對應的演算法有詳細的描述，其餘重要的議題如訊號擷取時間、硬體操作頻率等也做了深入的討論。擷取程序的偵測機率及硬體複雜度也使用軟體模擬驗證，並且有數據化的比較。

Within global positioning system (GPS) where acquisition is a signal synchronization process, to be more precisely, the purpose of acquisition is finding the code phase and Doppler frequency shift of visible satellites. Huge searching space of acquisition causes high complexity in both operational and hardware aspects. In the other hand, to improve the acquisition detection performance, both coherent and incoherent integration are needed, and these integration schemes induce memory requirement ascension, so the hardware demand is increased even more for acquisition process. In order to reduce the complexity of acquisition process, two hardware resource integration structures are proposed. For a typical practice code phase search in acquisition process, two hardware resources for coherent integration and correlation operation are needed: SRAM for coherent integration and shift register for correlation operation. The main idea of our design is integrating these two hardware resources together, using only one resource to achieve both coherent integration and correlation operation, so the hardware complexity of acquisition can be reduced with NO detection performance degradation. In the thesis, the hardware architectures and corresponding algorithms of the two proposed acquisition structures will be described. Important issues such as acquisition time, operation frequency will be discussed. The detection performance and hardware complexity are simulated and quantitatively analyzed.