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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳信樹 | |
dc.contributor.author | Hung-Wei Kevin Chen | en |
dc.contributor.author | 陳宏維 | zh_TW |
dc.date.accessioned | 2021-06-17T00:25:42Z | - |
dc.date.available | 2013-05-14 | |
dc.date.copyright | 2012-05-14 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-03-27 | |
dc.identifier.citation | [1] Wei-Chih Cheng, “A 1.2V High-Speed Single-Channel Pipeline A/D Converter,” NTU, GIEE, Master thesis, 2010
[2] B. Murmann, 'A/D Converter Trends: Power Dissipation, Scaling and Digitally Assisted Architectures,' IEEE CICC, pp. 105-112 Sept. 2008 [3] B. Murmann, 'ADC Performance Survey 1997-2011,' [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html [4] Dieter Draxelmayr, “A 6b 600MHz 10mW ADC Array in Digital 90nm CMOS,” IEEE ISSCC Dig. Tech. papers, pp. 264-265 Feb. 2004 [5] M. van Elzakker, et al. “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE ISSCC Dig. Tech. Papers, pp. 244-246, Feb. 2008. [6] B. E. Jonsson “A survey of A/D Converter performance evolution,” IEEE ICECS, pp. 766-769. Dec. 2010. [7] C.-K. Hung, et.al.“A 6-bit 1.6GS/s Flahs ADC in 0.18-μm CMOS with Reversed-Reference Dummy,” IEEE A-SSCC, pp. 335-338, Nov. 2006. [8] G. Keskin, et. al. “Exploiting Combinatorial Redundancy for Offset Calibration in Flash ADCs,” IEEE JSSC vol. 46 no.8 pp.1904-1918, Aug. 2011. [9] A. Verma and B. Razavi, ”A 10b 500MHz 55mW CMOS ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 3039-3050, Nov. 2009. [10] K.-W. Hsueh, et al, “A 1V 11b 200MS/s Pipelined ADC with Digital Background Calibration in 65nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 547-548, Feb. 2008. [11] D. Zhang, et. al. “Power Consumption Bounds for SAR ADCs,” IEEE ECCTD, pp.556-559, Aug. 2011 [12] Y.-Z. Lin, et. al. “A 0.9-V 11-bit 25-MS/s Binary Search SAR ADC in 90-nm CMOS,” IEEE A-SSCC, pp. 69-72, Nov. 2011. [13] V. Giannini, et al, “An 820μW 9b 40MS/s noise-tolerant dynamic-SAR ADC in 90nm digital CMOS,” IEEE ISSCC Dig.Tech. Papers, pp. 238—239, Feb. 2008. [14] A. Shikata, et al. “A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 262-263, Jun. 2011. [15] Dai Zhang, et al. “A 53-nW 9.12-ENOB 1-kS/s SAR ADC in 0.13-μm CMOS for medical implant device,” IEEE ESSCIRC, pp. 467-470, Sept. 2011. [16] S. Lee, et. al. “A 12b 5-to-50MS/s 0.5-to-1V Voltage Scalable Zero-Crossing Based Pipelined ADC,” IEEE ESSCIRC, pp. 355-358, Sept. 2011. [17] Klass Bult, “Embedded Analog-to-Digital Converters,” IEEE ESSCIRC, pp. 54-64, Sept. 2009. [18] M. Boulemnakher, et. al. “A 1.2V 4.5mW 10b 100MS/s Pipeline ADC in a 65nm CMOS,” IEEE ISSCC Dig. Tech. papers pp. 250-251 Feb 2008 [19] C. C. Liu, et. al. “A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” IEEE Symposium on VLSI Circuits, pp. 241-242, Jun. 2010. [20] S.-I. Chang, et. al. “BioBolt: A Minimally-Invasive Neural Interface for Wireless Epidural Recording by Intra-Skin Communication,” IEEE Symposium on VLSI Circuits, pp. 147-148, Jun. 2011. [21] Geert Van der Plas and Bob Verbruggen “A 150MS/s 133μW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC,” IEEE ISSCC Dig. Tech. papers pp. 242-243 Feb 2008 [22] Geert Van der Plas, et. al. “A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process,” IEEE ISSCC Dig. Tech. Papers, pp. 2310-2311, Feb. 2006. [23] T. Sepke, et. al. “Comparator-based switched-capacitor circuits for scaled CMOS technologies,” IEEE ISSCC Dig. Tech. papers pp. 812 – 821, Feb. 2006 [24] Lane Brooks and Hae-Seung Lee, “A Zero-Crossing-Based 8b 200MS/s Pipelined ADC,” IEEE ISSCC Dig. Tech. papers pp. 460-461, Feb. 2007 [25] S.-K. Lee et. al. “A 1.3μW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18um CMOS,” IEEE Symposium on VLSI Circuits, pp. 242-243, Jun. 2009. [26] B. P. Hershberg et. al. “A 1.4V Signal Swing Hybrid CLS-Opamp/ZCBC Pipelined ADC Using a 300mV Output Swing Opamp,” IEEE ISSCC Dig Tech Papers, pp. 302-303, Feb. 2010. [27] P. Schvan, et. al. “A 22GS/s 5b ADC in 0.13μm SiGe BiCMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 2340-2341, Feb. 2006. [28] Y. M. Greshishchev, et. al. “A 40GS/s 6b ADC in 65nm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 390-391, Feb. 2010. [29] Y.-H. Chung and J.-T. Wu, “A 16-mW 8-Bit 1GS/s Subranging ADC in 55nm CMOS,” IEEE Symposium on VLSI Circuits, pp. 128-129, Jun. 2011. [30] B. Verbruggen, et. al. “A 2.6mW 6b 2.2GS/s 4-times Interleaved Fully Dynamic Pipelined ADC in 40nm Digital CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 296-297, Feb. 2010. [31] J. Elbornsson, et. al. “Analysis of mismatch effects in a randomly interleaved A/D converter system,” IEEE TCAS-I, vol. 52, pp 465-476, Mar. 2005 [32] K. Kattmann and J. Barrow, 'A Technique for Reducing Differential Nonlinearity Errors in Flash A/D Converters,' IEEE ISSCC. Dig. Tech. Papers, pp. 170-171, Feb. 1991. [33] M. Choi and A. A. Abidi, “A 6-b 1.3-Gsample/s A/D Converter in 0.35-μm CMOS,” IEEE J. Solid-State Circuits, vol. 36 no.12 pp. 1847-1858, Dec. 2001. [34]J. Doernberg, P. R. Gray, and D. A. Hodges, 'A 10-bit 5-Msample/s CMOS two-step flash ADC,' IEEE J. Solid-State Circuits, vol.24, no.2, pp.241-249, Apr. 1989. [35] S. H. Lewis and P. R. Gray, “A pipelined 5-MSample/s 9-bit analog-to digital converter,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 954–961, Dec. 1987. [36] N. Fukushima et al., “A CMOS 40MHz 8b 105mW two-step ADC,” IEEE ISSCC Dig. Tech. papers, pp. 14 - 15, Feb. 1989. [37] P. M. Figueiredo et al., “A 90nm CMOS 1.2V 6b 1GS/s Two-Step Subranging ADC,” IEEE ISSCC Dig. Tech. papers, pp.568-570 Feb. 2006. [38] Y.-C. Lien and J. Lee, 'A 6-b 1-GS/s 30-mW ADC in 90-nm CMOS technology,' IEEE A-SSCC, pp.45-48, 3-5 Nov. 2008. [39] S. M. Louwsma et al., “A 1.35GS/s, 10b, 175mW Time-Interleaved AD Converter in 0.13μm CMOS,” IEEE J. Solid-State Circuits, vol. 42 No. 4 pp. 778-786 Apr. 2008. [40] Z. Cao, S. Yan, and Y. Li “A 32mW 1.25G 6b 2b/step SAR ADC in 0.13μm CMOS,” IEEE ISSCC Dig. Tech. papers, pp.542-543 Feb. 2008. [41] P. Schvan et al., “A 24GS/s 6b ADC in 90nm CMOS,” IEEE ISSCC Dig. Tech. papers, pp.544-545 Feb. 2008. [42] N. Kurosawa et al., “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuit Syst. I, vol. 48, No. 3 pp. 261-271, Mar. 2001. [43] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill Higher Education, pp 421-422, International edition 2001. [44] K. Matsui et al., “CMOS video filters using switched capacitor 14MHz circuits,” IEEE J. Solid-State Circuits, vol. SC-20, No.6 pp. 1096-1102 Dec. 1985. [45] G. Merckel, “A Simple Model of the Threshold Voltage of Short and Narrow Channel MOSFETs,” Solid State Electronics, Vol. 23, pp 1207-1213, Dec. 1980. [46] L. A. Lakers and J. J. Sanchez, “Threshold Voltage Model of Short Narrow and Small Geometry MOSFET s: a Review,” Solid State Electronics, Vol. 25, pp 621-641, July. 1982. [47] B.-M. Min et al., “A 69-mW 10-bit 80-MSample/s Pipeline CMOS ADC,” IEEE J. Solid-State Circuits, vol. 38 No.12 pp. 2031-2039 Dec. 2003. [48] S. Gupta et al., “A 1GS/s 11b Time-Interleaved ADC in 0.13-μm CMOS,” IEEE ISSCC Dig. Tech. papers, pp.2360- 2369 Feb. 2006. [49] C.-C. Hsu et al., “A 7b 1.1GS/s Reconfigurable Time-Interleaved ADC in 90nm CMOS,” Dig. Symp. VLSI Circuits, pp. 66-67 Jun. 2007. [50] B. Verbruggen et al., “A 2.2mW 5b 1.75GS/s Folding Flash ADC in 90nm Digital CMOS,” in IEEE Int. Solid-State Circuit Conf. Dig. Tech. Papers, pp.252-253 Feb. 2008. [51] K. Deguchi et al., “A 6-bit 3.5GS/s 0.9-V 98-mW Flash ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 43 No.10 pp. 2303-2310 Oct. 2008. [52] H. Lee, D. Hodges, and P. Gray, “A self-calibrating 15-bit CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. SC-19, pp.813-819, Dec. 1984 [53] A. Karanicolas, H. Lee, and K. Bacrania, “A 15-b 1Msample/s digitally self-calibrated pipeline ADC,” IEEE J. Solid-State Circuits, vol. 28, pp.1207-1215, Dec. 1993 [54] U. K. Moon and B. S. Song, “Background digital calibration techniques for pipelined ADCs,” IEEE T-CAS II, pp. 102-109, Feb. 1997. [55] B. Hernes et al.,”A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13 μm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 462-463, Feb. 2007. [56] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators,” IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1916-1926, Dec. 1992. [57] Y-K Chang, et. al. “A 8-bit 500-KS/s Low Power SAR ADC for Bio-Medical Application,” IEEE A-SSCC, pp.228-231, Nov. 2007. [58] J. Craninckx, et. al. “A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 246-248, Feb. 2007. [59] F. Kuttner, “A 1.2V 10b 20MSamples/s Non-Binary Successive Approximation ADC in 0.13 μm CMOS,” IEEE ISSCC Dig. Tech. Papers. pp. 176-177, 2002. [60] M. Hesener, et. al., “A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13μm CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 249-251, Feb. 2007. [61] P. Confalonieri, et. al., “A 2.7mW 1MSps 10b Analog-to-Digital Converter with Built-in Reference Buffer and 1LSB Accuracy Programmable Input Ranges,” Proc. ESSCIRC. pp. 255-258, Sept.2004. [62] M. G. Kim, et. al. “A 10MS/s 11-b 0.19mm2 Algorithmic ADC with Improved Clocking,” IEEE Symp. on VLSI, pp. 49-50, Jun.2006. [63] J. Kang, et. al. “A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13 μm CMOS,” IEEE Symp. on VLSI, pp. 240-241, Jun.2009. [64] I. F. Akyildiz Y. S. W. Su, and E. Cayirci, “Wireless sensor networks: A survey,” Comput. Netw., vol. 38, no. 4, pp. 393-422, Mar. 2002. [65] D. Niyato, E. Hossain, M. Rashid, and V. Bhargava, “Wireless sensor networks with energy harvesting technologies: A Game-Theoretic Approach to Optimal Energy Management,” Wireless Communications, IEEE, vol. 14, no. 4, pp. 90–96, Aug. 2007. [66] A. Wang and A. P. Chandrakasan “A 180mV FFT processor using sub-threshold circuit techniques,” IEEE ISSCC Dig. Tech. Papers, pp. 292-293, Feb., 2004. [67] J. Kwong et al., “A 65nm sub-Vt microcontroller with integrated SRAM and switched-capacitor DC-DC converter,” IEEE ISSCC Dig. Tech. Papers, pp. 318-319, Feb., 2008 [68] U. Wismar, D. Wisland, and P. Andreani, “A 0.2 V 0.44 μW 20 kHz analog to digital ΣΔ modulator with 57 fJ/conversion FoM,” IEEE ESSCIRC, pp. 187-190, Sept. 2006, [69] D. C. Daly and A. P. Chandrakasan “A 6-bit, 0.2 V to 0.9 V highly digital flash ADC with comparator redundancy,” IEEE J. Solid-State Circuit, vol. 44, no. 11, pp. 3030-3038, Nov. 2009. [70] J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewers, “A 0.5-V 1-μW successive approximation ADC,” IEEE J. Solid-State Circuit, vol. 38, no. 7, pp. 1261-1265, Jul. 2003. [71] G. Promitzer, “12-bit low-power fully differential switched capacitor noncalibrating Successive Approximation ADC with 1 MS/s” IEEE J. Solid-State Circuit, vol. 36, no. 7, pp. 1138-1143, Jul. 2001. [72] B. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuit, vol. 42, no. 4, pp. 739-747, Apr. 2007. [73] K. Pun, S. Chatterjee, and P. Kinget, “A 0.5-V 74-dB SNDR 25-KHz continuous-time delta-sigma modulator with a return-to-open DAC,” IEEE J. Solid-State Circuit, vol. 42, no. 3, pp. 496-507, Mar. 2007. [74] S. Gambini, and J. Rabaey, “Low-power successive approximation converter with 0.5 V supply in 90 nm CMOS,” IEEE J. Solid-State Circuit, vol. 42, no. 11, pp. 2348-2356, Nov. 2007. [75] J. Shen, and P. Kinget ,“A 0.5-V 8-bit 10-Ms/s pipelined ADC in 90-nm CMOS” IEEE J. Solid-State Circuit, vol. 43, no. 4, pp. 787-795, Apr. 2008. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66208 | - |
dc.description.abstract | 類比數位轉換器是自然界信號和數位訊號中間的橋樑。它在電子系統中是一個重要的電路。 類比數位轉換器的應用可以從通信系統到感應系統。低功耗,高轉換頻率和高精度是類比數位轉換器設計中的重要指標。在這篇論文中所提出的技術是用來提高類比數位轉換器的轉換效能,同時保持相同的轉換率和精準度。並實現於四個不同應用的類比數位轉換器。
第一個作品是一個6位元每秒十億次轉換的類比數位轉換器給超寬帶(UWB)和數據存儲系統。使用雙通道兩階架構,以取代傳統功耗較大的快閃架構。它實現在0.13微米的製程。在每秒十億次轉換頻率下,功耗49毫瓦,得到5.44的有效位元。第二個作品是10位元每秒三億兩千萬次轉換的類比數位轉換器給高寬頻的無線通信。此作品提出補償低增益運放的所產生的非線性誤差方式。它採用90奈米製程,消耗42毫瓦,每秒三億兩千萬次轉換,達到8.71 的有效位元。第三項作品是為低功耗無線通信所設計的12位元每秒一千萬次轉換的類比數位轉換器。它將子範圍的概念導入了循序漸進式類比數位轉換器,以降低數位類比轉換器所需求的穩定時間。它實現在0.13微米的製程,量測到功耗3微瓦在每秒一千萬次轉換下並獲得9.62的有效位元。最後的一個作品是超低工作電壓的10位元每秒十萬次轉換的類比數位轉換器,它應用於超低功耗傳感器。它包含電荷泵的取樣電路。然後共模偏壓輸出電壓設計等於工作電壓,來達成超低電壓工作。在0.35V工作電壓下,它在每秒十萬次轉換下消耗340奈瓦,並獲得8.71的有效位元。此FOM的結果是8.4fJ/conversion-step,是使用0.13微米製程中最低的結果。 | zh_TW |
dc.description.abstract | Analog to digital converter (ADC) is a bridge between nature signal and digital world. It is an important building block in electronic systems. The applications for ADC are from wireless communications to sensor nodes. Low power, high conversation rate, and high accuracy are the core specifications in the ADC design. In this dissertation, four ADC works are presented and they are used in specified applications. The techniques proposed in this dissertation are used to improve the ADC energy efficiency while maintaining conversion rate and accuracy.
The first work is a 6b 1GS/s ADC for ultra-wide-band (UWB) and data storage systems. Two-channel two-step architecture is proposed to replace conventional high power flash architecture. It dissipates 49mW and obtains 5.44 ENOB in a 0.13-um CMOS. The second work is a 10b 320MS/s ADC for high bandwidth wireless communication. A gain error calibration technique is presented to compensate non-linearity error caused by low gain OPAMPs. It consumes 42mW and achieves 8.71 ENOB in a 90-nm CMOS. The third work is a 12b 10MS/s ADC for low power wireless communication systems. A sub-range concept is adopted into the SAR architecture to reduce the DAC settling time. It dissipates 3mW and obtains 9.62 ENOB in the 0.13-um CMOS. The final work is a 10b 100KS/s ADC for ultra-low power sensor nodes. A charge pump S/H circuit and the DAC output common mode biased at VDD allow ultra-low voltage operation. It consumes 340nW and achieves 8.71 ENOB in the 0.13-um CMOS. The figure of merit of this ADC is 8.4fJ/conversion-step which achieves the lowest by 0.13-um CMOS process in paper reported. | en |
dc.description.provenance | Made available in DSpace on 2021-06-17T00:25:42Z (GMT). No. of bitstreams: 1 ntu-101-D95943004-1.pdf: 2571746 bytes, checksum: 741b528786ff7188b699996aa541ae22 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 摘要 I
Abstract II Table of Contents IV List of Figures VIII List of Tables XI Chapter 1 INTRODUCTION 1 ________________________________________ 1.1 Motivation 1 1.2 Thesis Overview 3 Chapter 2 REVIEW OF NYQUIST RATE A/D CONVERTER 7 ________________________________________ 2.1 Introduction 7 2.2 Performance Metris 7 2.2.1 Offset and Gain Error 7 2.2.2 Differential and Integral Nonlinearity (DNL, INL) 8 2.2.3 Signal-to-Noise Ratio 9 2.2.4 Total Harmonic Distortion 10 2.2.5 Spurious-Free Dynamic Range 10 2.2.6 Signal-to-Noise and Distortion Ratio 11 2.2.7 Effective Number of Bits 11 2.2.8 Figure of Merit 11 2.3 Architecture of Analog-to-Digital Converters 12 2.3.1 Flash Architecture 12 2.3.2 Two-Step and Sub-Range Architecture 14 2.3.3 Pipeline Architecture 16 2.3.4 Successive-Approximation Register Architecture 17 Chapter 3 ENERGY EFFICIENT ADC ISSUES AND DESIGN TRENDS 19 ________________________________________ 3.1 Introduction 19 3.2 Energy Efficient ADC Issues of Nyquist Rat ADC Architecture 22 3.2.1 Flash ADC Issues 22 3.2.2 Pipeline ADC Issues 22 3.2.3 SAR ADC Issues 23 3.3 Design Trends for Energy Efficiency 25 3.3.1 Low Voltage Trend 25 3.3.2 Technology Scaling Trend 27 3.3.3 Dynamic Design Trend 30 3.3.4 Time-interleaving Design Trend 31 3.4 Conclusion 33 Chapter 4 A 49mW 1GS/S 6b TWO-CHANNEL TWO-STEP A/D CONVERTER IN 0.13-um CMOS 34 ________________________________________ 4.1 Introduction 34 4.2 Proposed Architecture 36 4.2.1 Converter Architecture 36 4.2.2 Timing 38 4.2.3 MDAC Transfer Function 40 4.3 Circuit Implementation 42 4.3.1 Clock Feedthrough Disturbance in MDAC 42 4.3.2 Self-timing Switch 48 4.3.3 OPAMP 50 4.3.4 Comparator Latch 53 4.3.5 Clock Generator 54 4.4 Measurement Results 56 4.5 Conclusion 64 Chapter 5 A 42mW 320MS/S 10b GAIN ERROR CALIBRATED A/D CONVERTER IN 90-nm CMOS 64 ________________________________________ 5.1 Introduction 64 5.2 Self-Calibrated Algorithm 66 5.2.1 Feedback Factor 66 5.2.2 MDAC with Calibration Capacitor 68 5.2.3 Self-Calibrated Process 70 5.3 Circuit Implementation 76 5.3.1 ADC Block Diagram 76 5.3.2 Calibration Capacitor 77 5.3.3 OPAMP 79 5.4 Measurement Results 82 5.5 Conclusion 87 Chapter 6 A 3mW 12b 10MS/S SUB-RANGE SAR A/D CONVERTER IN 0.13-um CMOS 88 ________________________________________ 6.1 Introduction 88 6.2 Sub-Range Concept 90 6.2.1 Sub-range Coarse and Fine ADC Resolution Arrangement 90 6.2.2 Sub-range Capacitor Array 91 6.2.3 Sub-range SAR ADC Conversion Sequence 94 6.3 Proposed Architecture 97 6.4 Circuit Implementation 98 6.4.1 Analog Circuit 98 6.4.2 Pre-Amplifier 99 6.4.3 Overlapping Logic 100 6.4.4 Sub-range Capacitor Array Layout 102 6.5 Measurement Results 103 6.6 Conclusion 107 Chapter 7 A 0.2-0.6V 10b FULLY DIFFERENTIAL SAR ADC 108 ________________________________________ 7.1 Introduction 108 7.2 Proposed Architecture 111 7.3 Circuit Implementation for Low Voltage Operation 113 7.3.1 Two-stage Dynamic Comparator 113 7.3.2 Charge Redistribution Capacitor DAC 115 7.3.3 Charge Pump and Sampling Switches 117 7.3.4 Self-timing Loop and Pulse Generator 120 7.3.5 Successive Register Controller 124 7.4 Measurement Results 125 7.4.1 Operational Voltage Range and Power Dissipation 125 7.4.2 Static and Dynamic Performance 127 7.4.3 Performance Limitation 131 7.5 Conclusion 133 Chapter 8 CONCLUSION 135 ________________________________________ 8.1 Conclusion 135 Bibliography 137 ________________________________________ Appendix 146 ________________________________________ A.I A 10b Gain Error Calibrated A/D Converter Behavior Model 146 A.II A 12b 10MS/s Sub-Range SAR A/D converter Behavior Model 158 | |
dc.language.iso | en | |
dc.title | 高效能奈奎斯特取樣頻率類比數位轉換器 | zh_TW |
dc.title | Energy Efficient Nyquist Rate Analog to Digital Converters | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 博士 | |
dc.contributor.oralexamcommittee | 劉深淵,李泰成,林宗賢,蔡宗亨,李洪松 | |
dc.subject.keyword | 類比數位轉換器,兩階式類比數位轉換器,循序漸進式類比數位轉換器,管線式類比數位轉換器,低電壓類比數位轉換器,子範圍循序漸進式類比數位轉換器,雙通道類比數位轉換器, | zh_TW |
dc.subject.keyword | Analog to Digital Converter,Two-step ADC,SAR ADC,Pipeline ADC,Low Voltage ADC,Sub-range SAR ADC,Two-channel ADC, | en |
dc.relation.page | 165 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-03-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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