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標題: | 適用電力線通訊系統之高動態範圍及低增益錯誤可變增益放大器 A High Dynamic Range, Low Gain Error Programmable Gain Amplifier for Powerline Communication Systems |
作者: | Kai-Hsiang Chan 詹凱翔 |
指導教授: | 陳中平(Charlie Chung-Ping Chen) |
關鍵字: | 可程式化增益放大器,電力線通訊,低增益誤差,高動態範圍,多音頻功率比例,可重置, PGA,PLC,Low Gain Error,High Dynamic Range,MTPR,Reconfigurable, |
出版年 : | 2012 |
學位: | 碩士 |
摘要: | 在現今的社會中,網路通訊與生活密不可分,除了乙太網路與無線網路之外,電力線通訊將是家庭及辦公室新的方案。其優勢相對於乙太網路為使用既有的電力線當作傳輸媒介,以減少布線。相對於無線網路具有更佳的穩定性,且不會因為水泥鋼筋而造成訊號強弱不一。因此電力線通訊將會是未來通訊發展中重要的一環。
本論文提出針對家用電力線網路聯盟(HomePlug AV)規格提出兩顆低功率寬增益範圍可程式化增益放大器。本電路中使用粗調整及微調整的方式減少可變增益放大器的級數,以降低功率消耗及寬增益範圍。並且為了電路操作和增益變化穩定加入電流補償機制。接著,利用轉導單元以虛指數(pseudo-exponential)的方式完成對數線性化的增益特性。 第一顆單晶片以TSMC CMOS 0.18μm製成實作。由量測得到98.67dB (-24.26~74.41dB)的增益範圍和1.57dB的增益間距,在線性度的表現上,三階交調截取點(IIP3)和1dB壓縮點功率(P1dB)最大值分別為10.39dBm和1dBm。放大器最大增益時的頻寬為58MHz。整體電路最大操作功率為1.99mW,核心電路面積(core area)為0.225 x 0.13mm2。 第二顆晶片實現於TSMC CMOS 90nm製程,並整合於電力線通訊傳輸(PLC)的類比前端電路中,其中包括可程式化增益放大器、類比數位轉換器、電力線驅動器和數位類比轉換器。為提高傳輸速率,頻寬設計至373.79MHz,增益範圍為41.42dB (-20.921~20.499dB),增益間距也為更精準的0.32dB。訊號經由可變增益放大器與數位類比轉換器,可得到有效輸出位元數(ENOB)為7.3bits和訊號雜訊失真比(SNDR)為46dB。整體電路面積為2.63 x 2.52mm2,當中可程式化增益放大器的面積為0.15 x 0.11 mm2。 Todays, Internet communication such as Ethernet and wireless are inseparable with our daily life. Besides, Power-Line Communication (PLC) will be a new scheme for household and office. The wire cost benefits of PLC outweigh Ethernet due to PLC used original power line as transmission wire. Moreover, PLC system is more stable than wireless internet and is able to transmit signals without interference from walls. Therefore, PLC system will take an important role of internet communication in the future development. Two low power and wide gain range programmable gain amplifiers (PGAs) were designed for HomePlug AV standards. The coarse and fine tune skills are used in PGA design to reduce programmable gain stages, wide gain range and power consumption. For circuit operation purpose, the current compensation technique is used in PGA design to stabilize gain step. Furthermore, the linear-in-decibel gain characteristics are implemented by pseudo-exponential function with transconductor units. The first PGA integrated chip was fabricated in TSMC CMOS 0.18μm process. According to measurement results, the performance shows 1dBm P1dB, 10.39dBm IIP3, -24.26dB voltage gain at lowest gain mode, and 98.67dB gain range with 1.57dB resolution while consuming 1.99mW at 1.8-V supply voltage. The core area is 0.225 x 0.13mm2. The second PGA chip was fabricated in TSMC CMOS 90nm process, integrated into PLC system as an analog front-end (AFE) circuit. The PLC transceiver includes a programmable gain amplifier (PGA), an analog-to-digital converter (ADC), a line driver, and a digital-to-analog converter (DAC). To achieve higher data rate, the bandwidth and gain range were designed to be 373.79MHz, 41.42dB (-20.921~20.499dB) with 0.32dB resolution. In addition, the signal through PGA and ADC has 7.3bits ENOB and 46dB SNDR. The whole chip (PLC) area is 2.63 x 2.52mm2, and PGA area is 0.15 x 0.11 mm2. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/66158 |
全文授權: | 有償授權 |
顯示於系所單位: | 電子工程學研究所 |
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