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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65768完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 郭大維 | |
| dc.contributor.author | Ming-Chang Yang | en |
| dc.contributor.author | 楊明昌 | zh_TW |
| dc.date.accessioned | 2021-06-17T00:11:19Z | - |
| dc.date.available | 2017-07-20 | |
| dc.date.copyright | 2012-07-20 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-07-12 | |
| dc.identifier.citation | [1] Flash-memory Translation Layer for NAND flash (NFTL). M-Systems, 1998.
[2] Nitin Agrawal, Vijayan Prabhakaran, Ted Wobber, John D. Davis, Mark Manasse, and Rina Panigrahy. Design Tradeoffs for SSD Performance. In the USENIX Annual Technical Conference, pages 57–70, June 2008. [3] Amir Ban. Flash File System. US Patent 5,404,485. In M-Systems, April 1995. [4] Li-Pin Chang. On Efficient Wear Leveling for Large-scale Flash-memory Storage Systems. In the 2007 ACM symposium on Applied computing (SAC), 2007. [5] Yuan-Hao Chang and Tei-Wei Kuo. A Commitment-basedManagement Strategy for the Performance and Reliability Enhancement of Flash-memory Storage Systems. In the 46th ACM/IEEE Design Automation Conference (DAC), 2009. [6] H. Cho, D. Shin, and Y.I. Eom. KAST: K-Associative Sector Translation for NAND Flash Memory in Real-Time Systems. In DATE, 2009. [7] Raz Dan and Rochelle Singer. Implementing MLC NAND Flash Memory for Cost- Effective, High-capacity Memory. M-Systems, September 2003. [8] Alexandre P. Ferreira, Miao Zhou, Santiago Bock, Bruce Childers, Rami Melhem, and Daniel Moss. Increasing PCM Main Memory Lifetime. In the ACM/IEEE Design, Automation and Test in Europe (DATE), 2010. [9] Benoit Godard, Jean-Michel Daga, Lionel Torres, and Gilles Sassatelli. Evaluation of Design for Reliability Techniques in Embedded Flash Memories. In the ACM/IEEE Design, Automation and Test in Europe (DATE), 2007. [10] Aayush Gupta, Youngjae Kim, and Bhuvan Urgaonkar. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings. In ASPLOS, 2009. [11] H. Jo, J.-U. Kang, S.-Y. Park, J.-S. Kim, and J. Lee. FAB: flash-aware buffer management policy for portable media players. IEEE Trans. Consum. Electron., 52(2):485–493, May 2006. [12] S. Kang, S. Park, H. Jung, H. Shim, and J. Cha. Performance trade-offs in using nvram write buffer for flash memorybased storage devices. IEEE Trans. Comput., 58(6):744–758, Jun 2009. [13] Yangwook Kang and Ethan L. Miller. Adding Aggressive Error Correction to a High-Performance Compressing Flash File System. In the ACM International Conference on Embedded Software (EMSOFT), 2009. [14] H. Kim and S. Ahn. BPLRU: a buffer management scheme for improving random writes in flash storage. In USENIX Conference on File and Storage Technologies (FAST), 2008. [15] Jesung Kim, Jong Min Kim, Sam H. Noh, Sang Lyul Min, and Yookun Cho. A Space-Efficient Flash Translation Layer For CompactFlash Systems. IEEE Transactions on Consumer Electronics, Nov 2002. [16] Tei-Wei Kuo, Yuan-Hao Chang, Po-Chun Huang, and Che-Wei Chang. Special Issues in Flash. In the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2008. [17] S.-W. Lee, D.-J. Park, T.-S. Chung, D.-H. Lee, S. Park, and H.-J. Song. A log buffer-based flash translation layer using fully-associative sector translation. ACM Transactions on Embedded Computing Systems, 6(3), July 2007. [18] Muthukumar Murugan and David.H.C.Du. Rejuvenator: A static wear leveling algorithm for nand flash memory with minimized overhead. In MSST, 2011. [19] Dushyanth Narayanan, Austin Donnelly, and Antony Rowstron. Write Off-Loading: Practical PowerManagement for Enterprise Storage. ACM Transactions on Storage, 4:10:1–10:23, November 2008. [20] Veera Papirla and Chaitali Chakrabarti. Energy-Aware Error Control Coding for Flash Memories. In the ACM/IEEE Design Automation Conference (DAC), July 2009. [21] D. Park, B. Debnath, and D. Du. CFTL: A Convertible Flash Translation Layer Adaptive to Data Access Patterns. In SIGMETRICS, pages 14–18, June 2010. [22] Samsung Electronics. K9GAG08U0M 2G x 8bit NAND Flash Memory Data Sheet, September 2006. [23] A.J. Smith. Disk cache–miss ratio analysis and design considerations. ACM Transactions on Computer Systems (TOCS), 3(3):161–203, Aug 1985. [24] Chin-HsienWu and Tei-Wei Kuo. An Adaptive Two-level Mnagement for the Flash Translation Layer in Embedded Systems. In the IEEE/ACM Iinternational Conference on Computer-Aided Design (ICCAD), pages 601–606, 2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65768 | - |
| dc.description.abstract | 隨著儲存裝置容量的快速成長，設計快閃記憶體管理層之位址投射機制已儼然形成一個艱鉅的挑戰。不同於以往的設計，我們提出了一個和儲存裝置容量無關、但基於使用者之當前存取集合（稱為 working-set）來設計的位置投射機制。這個機制顯著地提升了系統效能並達到了小單位位址投射機制的存取速率。此外，我們也提出了一個簡單且可實施的方式來平均地使用快閃記憶體，並同時能提供快閃記憶體壽命估測之能力。最後，藉由一系列之實驗，我們驗證了所提出方法之有效性，並得到了令人振奮的結果。 | zh_TW |
| dc.description.abstract | Address mapping for flash devices has been a challenging design problem for controllers because of the rapidly growing device capacity. Different from the past work, a capacity-independent address mapping scheme that only depends on users' access data set, referred to as working set, is proposed. As a result, fine-grained address mapping is achieved with significant performance boosting, compared to the past work. In addition, a simple but practical wear-leveling design is proposed with the capability in lifetime estimation of flash devices. The proposed scheme was evaluated by a series of experiments with encouraging results. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-17T00:11:19Z (GMT). No. of bitstreams: 1 ntu-101-R99944005-1.pdf: 2769971 bytes, checksum: ecccaab4acc5249febf5ec0bf1943e72 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | Abstract in Chinese v
Abstract vii Acknowledgment ix Contents xi List of Figures xiii List of Tables xiv 1 Introduction 1 2 System Architecture and Motivation 5 3 AWorking-Set-Based Address Mapping Scheme 10 3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 Run-Length Address Mapping Structure for Out-Place Area Management 13 3.3 Marching-Based Hot Data Gathering Strategy . . . . . . . . . . . . . . . 16 3.3.1 The Handling of Read/Write Requests . . . . . . . . . . . . . . . 17 3.3.2 Marching-Based Garbage Collection . . . . . . . . . . . . . . . . 21 3.4 Remark: Fast Initialization and Crash Recovery . . . . . . . . . . . . . . 26 4 Performance Evaluation 29 4.1 Metrics and Experiment Setup . . . . . . . . . . . . . . . . . . . . . . . 29 4.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.2.2 Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2.3 Various RAM and Capacity . . . . . . . . . . . . . . . . . . . . 33 4.2.4 RAM Space Requirement . . . . . . . . . . . . . . . . . . . . . 35 5 Conclusion 36 Bibliography 39 Curriculum Vitae 43 Publication List 45 | |
| dc.language.iso | zh-TW | |
| dc.subject | 效能 | zh_TW |
| dc.subject | 當前存取集合 | zh_TW |
| dc.subject | 儲存系統 | zh_TW |
| dc.subject | 快閃記憶體 | zh_TW |
| dc.subject | Working set | en |
| dc.subject | storage system | en |
| dc.subject | flash memory | en |
| dc.subject | performance. | en |
| dc.title | 基於當前存取集合之超大容量快閃記憶體位址投射 | zh_TW |
| dc.title | Working-Set-Based Address Mapping for Ultra-Large-Scaled Flash Devices | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 施吉昇,張原豪,陳銘憲,洪士灝 | |
| dc.subject.keyword | 當前存取集合,儲存系統,快閃記憶體,效能, | zh_TW |
| dc.subject.keyword | Working set,storage system,flash memory,performance., | en |
| dc.relation.page | 45 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-07-12 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
| 顯示於系所單位： | 資訊網路與多媒體研究所 | |
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