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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 簡韶逸(Shao-Yi Chien) | |
| dc.contributor.author | Yu-Sheng Lin | en |
| dc.contributor.author | 林裕盛 | zh_TW |
| dc.date.accessioned | 2021-06-16T23:39:46Z | - |
| dc.date.available | 2021-02-26 | |
| dc.date.copyright | 2020-02-26 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-02-19 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/65382 | - |
| dc.description.abstract | 近年來,深度學習技術在電腦視覺、自然語言處理、人工智慧等領域取得了極大的成功。在這些應用中大量使用了平行處理技術,提高運算性能。而在深度學習平行處理架構中,最大的一個挑戰是把資料從晶片外部移動到處理單元中。這是因為電晶體密度提昇的速度,遠遠快於記憶頻寬加大的速度。本論文中,我們提出一個數學方法,可以有效地將優化各種應用的技術套用於不同平行處理架構。我們發現在平行處理中,可以將資料搬移視為一種在記憶體層級中張量的轉換,因此就可以用數學描述多種記憶體優化技術。我們稱前述的張量轉換為「MERIT 轉換」,其不只可以適用於深度學習中,也適用對許多傳統的機器學習以及電腦視覺運算。此外「MERIT 轉換」可以對應到既存的向量處理架構上,透過這個轉換,我們能將許多常見的應用轉換為 GPU 上的 MERIT 表示法,可以用更少的程式碼提昇高達 20 倍的執行速度。我們也用這個轉換的原理設計了專用硬體架構 VectorMesh 來執行這個轉換。在這個架構中,處理單元被組成一個向量單元,透過佇列進行向量對向量的直接交換。除了常見的卷積網路、矩陣乘法外,VectorMesh 也支援多種深度學習技術例如次像素卷積或是相關性層,並且跟其他更專用的處理器有同等的能源以及面積效率。 | zh_TW |
| dc.description.abstract | Deep learning has achieved great success in fields such as computer vision, natural language processing, and artificial intelligence, and many of these applications utilize parallel processing to achieve high performance. One of the most significant challenges for optimizing deep learning applications on a parallel processing architecture is the data movement from the off-chip storage to processing elements (PEs) since the density of logic gates always grows much faster than memory bandwidth. In this dissertation, we propose a mathematical formulation that is useful for transferring the application optimization knowledge across computing platforms. We discover that in parallel processing, the data movement can be viewed as tensor transforms across memory hierarchies, making it possible to describe many memory optimization techniques mathematically. Such transform, which we call Memory Efficient Ranged Inner-product Tensor (MERIT) transform, can be applied to not only DNN tasks but also many traditional machine learning and computer vision computations. Moreover, the tensor transform can be readily mapped to existing vector processor architectures. With such transform, we can convert many popular applications into a succinct MERIT notation on CUDA GPUs, speeding up GPU kernels up to 20 times while using only half as many code tokens. We also use the principle of the proposed transform to design an ASIC architecture called VectorMesh. Its PEs are grouped as vectors, with FIFOs between the vectors to facilitate data exchange. VectorMesh supports various DNN tasks such as subpixel CNN and correlation layer, as well as other computer vision tasks while providing comparable area and power efficiency to dedicated DNN ASICs. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T23:39:46Z (GMT). No. of bitstreams: 1 ntu-109-D01943032-1.pdf: 4381976 bytes, checksum: 2367e767e313e31747104545236e2c79 (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | Abstract i
List of Figures vii List of Tables xi 1 Introduction 1 1.1 Conquering the Memory Bound 3 1.2 MERIT: A Tensor-centric Methodology 6 1.3 Thesis Statements and Contributions 11 1.4 Related Publications 12 1.5 Dissertation Organizations 12 2 The MERIT Tensor Transform 15 2.1 From Workloads to MERIT 15 2.1.1 Matrix Multiplication 16 2.1.2 Convolution Neural Network 17 2.1.3 Correlation Layer 19 2.1.4 An Example: AlexNet CONV1 in MERIT 20 2.2 Tensor for Buffer Management 20 2.2.1 Examples: Analyzing Buffer Sizes With MERIT 25 2.3 PE Group Scheduling 25 2.4 Operator Tensor and SIMD 30 3 Efficient MERIT Transform on GPUs 31 3.1 Avoid Bank Conflict on Shared Memory 32 3.2 Strategy-Based Tensor Product 33 3.3 Register Tiling 36 4 Efficient MERIT Transform on ASICs 39 4.1 Overview the VectorMesh Architecture 39 4.2 Sharing Tensors via FIFOs with MERIT 43 4.3 Efficient Memory Distribution Circuit with MERIT 48 4.4 SIMD for the Tensor Product 58 4.5 Implementation Details 60 4.5.1 Design Choices 60 4.5.2 Hardware for Data Movement and Address Calculation 61 4.6 Architectural Comparisons to State-of-the-arts 63 5 Experiments 71 5.1 GPU Code Size Reduction with MERIT 71 5.2 Performance Evaluation 71 5.3 Limitations of MERIT on GPUs 73 5.4 Chip Implementation Results 74 5.5 Bandwidth and Energy Saving by FIFOs 76 6 Related Works 79 6.1 High Performance DNN Processing 79 6.1.1 Parallel DNN and CNN Processing on GPUs 79 6.1.2 Dedicated Hardware for DNN and CNN 79 6.2 DNN Architectural Comparisons 81 6.3 Computation Abstraction 82 7 Conclusions 85 8 Appendix 87 8.1 An Example: MERIT for a Complete CNN 87 Reference 97 | |
| dc.language.iso | en | |
| dc.title | 張量本位之平行運算記憶體搬運優化方法論 | zh_TW |
| dc.title | A Tensor-centric Methodology for Optimizing Data Movement on Parallel Processing Hardware | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-1 | |
| dc.description.degree | 博士 | |
| dc.contributor.coadvisor | 陳維超(Wei-Chao Chen) | |
| dc.contributor.oralexamcommittee | 梁伯嵩(Bo-Song Liang),黃朝宗(Chao-Zong Huang),楊家驤(Jia-Xiang Yang),楊佳玲(Jia-Ling Yang),唐文力(Wen-Li Tang) | |
| dc.subject.keyword | 平行處理,通用圖形處理器,深度學習加速器,張量轉換,類神經網路, | zh_TW |
| dc.subject.keyword | parallel processing,general-purpose graphics processing unit (GPGPU),deep learning accelerator (DLA),tensor transform,neural network, | en |
| dc.relation.page | 106 | |
| dc.identifier.doi | 10.6342/NTU202000520 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-02-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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