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標題: | 寬頻除頻器和數位校正之射頻電路的設計和分析 Design and Analysis of Wide Bandwidth Frequency Divider and Digital-Calibrated RF Circuit |
作者: | Yen-Hung Kuo 郭彥宏 |
指導教授: | 黃天偉(Tian-Wei Huang) |
關鍵字: | 金氧半導體,注入鎖定除頻器,米勒除頻器,數位校正電路,隔離器,連續波頻率調變,前饋,電流模式邏輯, CMOS,injection-locked frequency divider (ILFD),Miller divider,digital calibrated circuit,isolator,frequency modulated continuous wave (FMCW),feedforward,current-mode logic (CML), |
出版年 : | 2012 |
學位: | 博士 |
摘要: | 寬頻的微波和毫米波有利於傳輸高速資料,所以高速的無線傳輸很適合應用在微波及毫米波頻段上。 很多高資料量的應用,例如下一代的電話通信(4G-LTE)和短距離雲端通訊(60GHz)都使用了寬頻帶來傳輸。 因此,為了傳輸寬頻的信號,設計高速、寬頻的本地振盪信號源是今日在設計無線收發機的一個重要的課題。 然而,設計一個高速、寬頻的本地振盪信號源並不容易。 它的速度和頻寬將會被高頻的寄生效應、輸出頻率和參考頻率的高比值、以及製程變異所限制。 這些設計上的瓶頸須於頻率產生器裡的除頻器中突破。
在高速除頻器的使用上,通常是採用注入鎖定除頻器和米勒除頻器此兩種的動態除頻器。但動態除頻器的缺點是頻寬較窄。 因此,頻寬增加的技術已經在前人的文獻中研究過,並且分別在注入鎖定除頻器達到42%、在米勒除頻器達到28%的頻寬。 然而,這樣的頻寬在加上製程、電壓、溫度的變異時還是有所不足。 所以,本論文的目的在於提供寬頻、高除數的除頻器、以及提供對變異較不敏感的數位輔助之射頻電路。 為了不對製程變異敏感,本論文提出寬頻的疊接式的注入鎖定除頻器和切頻的米勒除頻器。 寄生效應在兩個提出的除頻器中都有所設計和分析。 除了分析寄生效應外,數位輔助的技術也運用在切換頻帶的米勒除頻器上。 再者,數位電路亦整合於連續波調頻的隔離器中,來驗証數位校正的能力和提高可靠度。 所設計、分析的第一個電路是一個寬頻、除四的除頻器。 其中,疊接的電流模式-注入鎖定除頻器有較少的寄生效應且功耗較低。 所提出的電路操作頻率在0 dBm注入功率下可以從13.5到30.5 GHz,有77.3%的頻寬,是使用0.13微米的金氧半導體,而功耗為7.3 毫瓦。 第二個討論的電路是以0.18微米實現,數位輔助寬頻的米勒除頻器。 使用偵測功耗而非偵測頻率的方式,可以減少複雜度和提升電路的切頻效率。 所提出的電路可在8.2到14.8 GHz 操作,有57.4%的頻寬。功耗為12毫瓦。 最後,應用於連續波調頻的數位校正隔離器也會在本論文中分析。 其中,提出的數位校正可以在正饋電路上自動找到最佳衰減值,來達到高發射至接收端的隔離度。使用0.18微米的製程,本電路在13.5毫瓦的功耗下,隔離度可改善至27.3 dB 而發射至天線的輸出線性功率則大於 +13.5 dBm。 For wireless high-data-rate communication, the wideband frequency resource which allocate at microwave and millimeter wave frequency is essential. Many applications such as the next generation 4G-LTE backhaul link and the short-range Cloud communications at 60 GHz utilize wide-band frequency resources for high data rate. Therefore, the design of wide-band high-speed local oscillator (LO) is an important issue in today’s wireless transceiver. However, the design of high-speed wide-band LO is not an easy task. The parasitic effect, large division ratio between output frequency and reference frequency, process variation make the bandwidth and speed limited. These design bottlenecks need to be solved in frequency divider which is the key component on the feedback path of frequency synthesizer. For high-speed operation, the dynamic frequency divider such as injection-locked frequency divider (ILFD) and Miller divider can be used. The dynamic frequency divider has drawback of narrow bandwidth. Therefore, the bandwidth-enhanced techniques proposed in previously published work achieve 42% and 28% bandwidth for ILFD and Miller divider, respectively. Nevertheless, the bandwidth is not wide enough to tolerance the process, voltage, and temperature (PVT) variations. Therefore, the purpose of this dissertation is to develop wideband, large division ratio frequency divider and to develop PVT-tolerant digital-assisted circuit for RF integrated circuits. To tolerant the PVT variation, the wideband cascoded ILFD and band-switched Miller divider are proposed. Parasitic effect is carefully analyzed in both frequency dividers. In addition to analysis of parasitic, the digital-assisted technique is used in band-switched Miller divider to simplify complexity and to increase speed of the calibration circuit. Furthermore, reliable digital circuit is also integrated with isolator of frequency-modulated continuous wave (FMCW) front-end to demonstrate the performance-enhanced digital calibration. The first circuit presented in this dissertation, is the wide-band, divide-by-4 frequency divider. A cascoded current-mode logic and ILFD has less parasitic effect and consumes less dc power. The cascoded frequency divider is implemented in 0.13-μm CMOS technology and has a 77.3% frequency locking range from 13.5 to 30.5 GHz at injection power of 0 dBm while consuming 7.3-mW dc power. A bandwidth-enhanced technique for Miller divider is presented in this dissertation. By detecting the power rather than the frequency, the proposed digital algorithm is high efficiency and is low complexity. The digital-assisted frequency divider is implemented in 0.18-μm CMOS technology which shows 57.4 % bandwidth from 8.2 to 14.8 GHz at input power of 0 dBm while consuming 12-mW dc power. Finally, a digital-calibrated isolator for FMCW RFIC is described in this dissertation. The proposed transmitter-to-receiver isolator has digital-calibrated circuits to find the optimal attenuation in the feedforward isolator automatically. The proposed isolator is implemented in 0.18- |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64945 |
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顯示於系所單位: | 電信工程學研究所 |
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