高速加法器之設計方法與高速測試技術暨有線與無線傳送接收前端設計

Abstract

本論文完整包含了晶片的核心，與晶片對外的通訊介面，可以分為二個主要部分：(1) 高速加法器的設計方法與高速測試技術(2) 有線與無線傳送接收前端設計。 第一部分：數位處理器的效能依賴於加法器的速度，本論文包含了加法器的設計方法與高速測試技術：(1) 自從超大型積體電路的製程技術進入深次微米之後，影響系統效能的因素已經由原先的閘級延遲改變為連線延遲，因此如何減少連線延遲便成為提昇加法器的一個重要目標。(2) 高速測試可以偵測轉態錯誤，但是在過去加法器僅可以做低速功能測試，無法做有效率的高速測試，以致無法保證高速操作下是否可以正常運作。 在本篇論文裡，我們完整探討了如何設計加法器，以及如何有效率的測試加法器：(1) 本篇論文分析了在0.35um、0.18um、90nm 不同製程下，連線延遲的影響將逐漸大於閘級延遲。所以使用混合radix-4 sparse-4 tree 設計方法將比傳統Radix-2 架構有更小的延遲時間181 ps。並藉由時脈落後骨牌電路可以達到更快的操作頻率。此設計方法並可應用於更高位元加法器(>32-bit)。(2) 本篇論文率先在加法器上使用了高速虛擬完全測試技術，僅需要54K 組測試向量即可達到100% 單一黏著性錯誤涵蓋率, 與僅需要13M 組測試向量即可達到100% 轉態錯誤涵蓋率。藉由延遲鎖定迴路(DLL) 量測技術，可以量測延遲時間與達到速度分 類。 第二部分：在提昇晶片中數位處理器的運算速度之後，但晶片間的通訊卻無法達到相對的速度。本論文將從二方面來探討傳送接收器：有線通訊與無線通訊。(1) 隨著多媒體科技的發展，有線高速傳輸成為各種電路中不可或缺的一部分。再者由於手提電子設備的需求，低功率考量也成為重要的一個環節。因此如何設計出高速低功率的傳送接收器成為現今重要的議題。(2) 人們之間的溝通模式由於無線通訊科技的便利而有巨大的改變。除了手機之外，近年來無線資料傳輸模式亦引起相當的注意。在無線通訊系統內，接收前端必須提供足夠的訊號強度與線性度，將電路中的雜訊降到最低以維持訊號的品質。 本篇論文提出了如何設計有線通訊與無線通訊：(1) 本篇論文描述了一個高速且低功率損耗電容耦合傳送接收器，將資料透過75-fF 電容經由10 公分的FR4傳輸線來傳輸，最大可到達12-Gb/s 的傳輸速度。傳送器與接收器分別僅消耗21.3 mW 和13.5 mW 的功率。(2) 本篇論文提出整合單端轉雙端與電流重複利用的二級線性度改善架構，並將整個接收前端視為一體納入考量設計，達到了極好的放大增益與線性度。

This dissertation presents one of the tops in microprocessor design and communication design between chips. Two parts are discussed: (1) the design methodology and at-speed test technique for high-performance adders, (2) wire and wireless frontend transceivers. The adder, which directly affects the overall performance, is the most important unit in the microprocessors. This dissertation discusses two aspects of adder design:(1) In deep sub-micron technology, interconnect wire delay will be the bottleneck for high performance adders instead of gate loading. Therefore, reducing interconnect wire delay is important to improve adder performance. (2) At-speed testing detects transition faults. But in the past, only function testing is applied to adder testing. It cannot be used to validate the operating frequency and latency in real silicon. In the dissertation, we discuss how to design an adder and how to test an adder efficiently: (1) this dissertation shows that the effect of interconnect wire delay will increase in deep sub-micro technology between 0.35-um, 0.18-um, and 90-nm technologies. Therefore, this dissertation uses a new design methodology of 64-bit hybrid radix-4 sparse-4 tree with 181-ps latency, which is faster than the one based on conventional topology. Moreover, by using clock-delayed (CD) footless domino logics, the proposed adder achieves the 6.4-GHz operating frequency in a 90-nm CMOS technology. This design methodology can also be used in high-order adders (>32-bit). (2) This dissertation is the first case using the pseudo-exhaustive testing (PET) for high-speed high-order adders. The at-speed pseudo-exhaustive testing guarantees 100% coverage by only 54K patterns for single stack-at faults. With the delay-locked loop (DLL) latency-measurement technique, speed binning of high performance CPUs is now possible. However, after improving the microprocessor performance, the chip communication cannot achieve corresponding high speed. Thus, this dissertation discusses two important aspects of communications: (1) With the popularity of the media technology, high speed chip-to-chip transceivers are the critical circuitry in many systems such as USB 3.0 (5 Gbps) and HDMI 1.4 (3.5 Gbps). Moreover, for the mobile applications, low power consumption is also an important factor. (2) The convenience comes with the wireless technology has drastically changed the way people communicate. Other than cellular phone services, the wireless data communication has attracted great attention in recent years. In the transceiver design of a wireless LAN system, the front-end receiver must provide sufficient signal amplification and linearity while maintain minimum noise to ensure the quality of the received signal. In this dissertation, we discuss the design of the wire and wireless communication technique: (1) This dissertation describes a low-power and high-speed chip-to-chip communication for high density interconnects. A 12-Gb/s front-end transceiver is demonstrated through a wire-bonded AC coupled interconnect (ACCI) channel with 75-fF coupling capacitors, across 10-cm FR4 micro-strip lines. (2) This dissertation also presents a two-stage linearity-enhancement technique in the wireless front-end receiver. The linearization technique integrate single-to-differential and current-reused architecture to achieve high linearity and high gain.