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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/6455完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Chieh-Fan Lai | en |
| dc.contributor.author | 賴傑帆 | zh_TW |
| dc.date.accessioned | 2021-05-17T09:13:57Z | - |
| dc.date.available | 2014-08-28 | |
| dc.date.available | 2021-05-17T09:13:57Z | - |
| dc.date.copyright | 2012-08-28 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-17 | |
| dc.identifier.citation | [1] A. Varzaghani and C. K. Yang, “A 600-MS/s 5-Bit Pipeline
A/D Converter Using Digital Reference Calibration” IEEE J. Solid-State Circuits, vol. 41, no.2, pp. 310–319, February 2006. [2] E. Iroaga and B. Murmann, “A 12-Bit 75-MS/s Pipelined ADC Using Incomplete Settling” IEEE J. Solid-State Circuits, vol. 42, no.4, pp. 748–756, April 2007. [3] B. R. Gregoire and U. Moon, “An Over-60 dB True Rail-to- Rail Performance Using Correlated Level Shifting and an Opamp With Only 30 dB Loop Gain” IEEE J. Solid-State Circuits, vol. 43, no.12, pp. 2620–2630, December 2008. [4] N. Sasidhar, Y. Kook, S. Takeuchi, K. Hamashita, K. Takasuka, P. K. Hanumolu and U. Moon, “A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback” IEEE J. Solid-State Circuits, vol. 44, no.9, pp. 2392-2401, September 2009. [5] P. Y. Wu, V. S. Cheung, and H. C. Luong, “A 1-V 100-MS/s 8-bit CMOS Switched-opamp Pipelined ADC Using Loading- free Architecture” IEEE J. Solid-State Circuits, vol. 42, no.4, pp. 730-738, April 2007. [6] Y. Huang and T. Lee, ” A 10b 100MS/s 4.5mW Pipelined ADC with a Time Sharing Technique” IEEE International Solid- State Circuits Conference, February 2010. [7] L. Brooks and H. Lee, “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC” IEEE J. Solid-State Circuits, vol. 44, no.12, pp. 3329–3343, December 2009. [8] I. Ahmed, J. Mulder and D. A. Johns, “A Low-power Capacitive Charge Pump Based Pipelined ADC” IEEE J. Solid-State Circuits, vol. 45, no.5, pp. 1016–1027, May 2010. [9] B. Hershberg, S. Weaver, K. Sobue, S. Takeuchi, K. Hamashita and U. Moon, ”A 61.5dB SNDR Pipelined ADC Using Simple Highly-Scalable Ring Amplifiers” Symposium on VLSI Circuits Digest of Technical Papers, June 2012. [10] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters. Wiley-IEEE Press, 1995 [11] C. J. Tseng, H. W. Chen, W. T. Shen, W. C. Cheng and H. S. Chen, “A 10-b 320-MS/s Stage-Gain-Error Self- Calibration Pipeline ADC” IEEE J. Solid-State Circuits, vol. 47, no.6, pp. 1334–1343, June 2012. [12] D. L. Shen and T. C. Lee, “A 6-bit 800-MS/s Pipelined A/D Converter With Open-Loop Amplifiers” IEEE J. Solid- State Circuits, vol. 42, no.2, pp. 258–268, February 2007. [13] A. S. Sedra and K. C. Smith, Microelectronic Circuits. Oxford University Press, 2004. [14] O. Stroeble, V. Dias and C. Schwoerer, ”An 80MHz 10b Pipeline ADC with Dynamic Range Doubling and Dynamic Reference Selection” IEEE International Solid-State Circuits Conference, February 2004. [15] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with A Monotonic Capacitor Switching Procedure” IEEE J. Solid-State Circuits, vol. 45, no.4, pp. 731–740, April 2010. [16] B. Razavi, Principles of Data Conversion System Design. Wiley-IEEE Press, 1995. [17] K. L. Lee and R. G. Meyer, “Low-Distortion Switched- Capacitor Filter Design Techniques” IEEE J. Solid-State Circuits, vol. 20, no.6, pp. 1103–1113, December 1985. [18] B. Razavi and B. A. Wooley, “Design Techniques for High-Speed, High-Resolution Comparators” IEEE J. Solid- State Circuits, vol. 27, no. 12, pp. 1916-1926, December 1992. [19] A. Varzaghani and C. K. Yang, “A 4.8 GS/s 5-bit ADC- Based Receiver with Embedded DFE for Signal Equalization” IEEE J. Solid-State Circuits, vol. 44, no. 3, pp. 901–915, March 2009. [20] T. Sundstrom, C. Svensson, “A 2.4 GS/s, Single-Channel, 31.3 dB SNDR at Nyquist, Pipeline ADC in 65 nm CMOS” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1575– 1584, July 2011. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/6455 | - |
| dc.description.abstract | 本論文採用了不完全趨穩的技巧，提出了背景調整取樣時間校正來實現一個
六位元、每秒十億次取樣的導管式類比數位轉換器。不完全趨穩的技巧伴隨著背 景調整取樣時間校正能夠降低類比數位轉換器中運算放大器對於增益和頻寬的需 求從而降低運算放大器的功率消耗。 本晶片使用台積電 65nm CMOS 一般製程製作。根據量測結果，在1 GS/s 的 轉換率下的DNL 和INL 分別為+0.72/-0.68 LSB 和+0.76/-0.68 LSB。在輸入頻率為499.0 MHz 且在1 GS/s 的轉換率下時，SNDR 和SFDR 分別為33.39 dB 和41.03dB。然而在輸入頻率為9.7 MHz 且在900 MS/s 的轉換率下時，SNDR 和SFDR 分別為35.17 dB 和49.50 dB。在1 V 的電壓和1 GS/s 的轉換率下的功率消耗為62 mW。全部的晶片面積大小為0.89 mm2，然而主動電路所占的面積只有0.30 mm2。 | zh_TW |
| dc.description.abstract | This thesis adopts incomplete-settling technique and proposes background sampling-point calibration to realize 6-bit, 1GS/s pipelined ADC. Incomplete-settling technique with proposed background sampling-point calibration allows low-gain and low-bandwidth opamp to be used and lowers the power consumption of opamp.
This prototype ADC is fabricated in TSMC 65nm CMOS general-process. According to measurement results, this prototype ADC exhibits DNL of +0.72/-0.68 LSB and INL of +0.76/-0.68 LSB at sampling rate of 1 GS/s. SNDR and SFDR are 33.39 dB and 41.03 dB at 1 GS/s with 499.0 MHz input frequency. But at 900 MS/s with 9.7 MHz input frequency, SNDR and SFDR are 35.17 dB and 49.50 dB. The power consumption is 62 mW at 1 V supply voltage and 1 GS/s sampling rate. Active area is 0.30 mm2, and whole chip with pads occupies 0.89 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-05-17T09:13:57Z (GMT). No. of bitstreams: 1 ntu-101-R98943131-1.pdf: 1138622 bytes, checksum: 6bffbd082a9688abaf39a980b4fb5839 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 摘要.......................................................I
Abstract..................................................II Contents.................................................III List of Figures..........................................VII List of Tables............................................XI Chapter 1 Introduction.....................................1 1.1 Motivation.............................................1 1.2 Thesis Organization....................................2 Chapter 2 Fundamentals of ADC..............................3 2.1 Introduction...........................................3 2.2 Performance Metrics....................................3 2.2.1 Static Performance...................................3 2.2.2 Dynamic Performance..................................5 2.3 ADC Architectures......................................8 2.3.1 Flash ADC Architecture...............................8 2.3.2 Successive-approximation ADC Architecture............9 2.3.3 Pipelined ADC Architecture..........................11 2.3.4 Continuous-time Delta-sigma ADC Architecture........12 2.4 Summary...............................................13 Chapter 3 Proposed Background Sampling-point Calibration for for Pipelined ADC Using Incomplete-settling Technique.......................................15 3.1 Introduction..........................................15 3.2 Incomplete-settling Technique.........................19 3.2.1 Concept of Incomplete-settling Technique............19 3.2.2 Prior Work 1: Digital Reference Calibration.........20 3.2.3 Prior Work 2: Digital Signal Processing Calibration.22 3.3 Proposed Pipelined ADC Architecture and Background Sampling-point Calibration............................24 3.3.1 Pipelined ADC Architecture..........................24 3.3.2 Background Sampling-point Calibration...............25 3.4 Non-Idealities of Background Sampling-point Calibration. ......................................................28 3.4.1 Opamp Slewing and DC Gain, Unit Gain Bandwidth Variation with Output Swing.........................30 3.4.2 Discrete Sampling-point and Clock Jitter............33 3.4.3 Sampling Attenuation................................34 3.5 Summary...............................................37 Chapter 4 Proposed Building Blocks and Circuit Implementation..................................38 4.1 Introduction..........................................38 4.2 Building Blocks and Circuit Implementation............38 4.2.1 MDAC................................................38 4.2.2 Sub-ADC.............................................50 4.2.3 Clock Generator.....................................52 4.2.4 Calibration Circuits................................56 4.2.5 Timing Arrangement..................................66 4.3 Overall ADC Simulation Results........................70 4.3.1 Static Performance..................................70 4.3.2 Dynamic Performance.................................71 4.4 Summary...............................................72 Chapter 5 Measurement Results.............................73 5.1 Introduction..........................................73 5.2 Floor Plan and Layout.................................73 5.3 PCB design............................................77 5.4 Test Setup............................................79 5.5 Measurement Results...................................80 5.5.1 Static Performance..................................81 5.5.2 Dynamic Performance.................................83 5.6 Summary...............................................88 Chapter 6 Conclusions.....................................90 Bibliography..............................................91 | |
| dc.language.iso | en | |
| dc.title | 一個使用不完全趨穩技巧伴隨著背景調整取樣時間校正的高速導管式類比數位轉換器 | zh_TW |
| dc.title | A High-speed Pipelined ADC Using Incomplete-settling Technique with Background Sampling-point Calibration | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢,郭建宏 | |
| dc.subject.keyword | 類比數位轉換器,背景校正,導管式,不完全趨穩, | zh_TW |
| dc.subject.keyword | ADC,background calibration,pipelined,incomplete-settling, | en |
| dc.relation.page | 94 | |
| dc.rights.note | 同意授權(全球公開) | |
| dc.date.accepted | 2012-08-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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|---|---|---|---|
| ntu-101-1.pdf | 1.11 MB | Adobe PDF | 檢視/開啟 |
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