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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64557完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李泰成 | |
| dc.contributor.author | Jia-An Jheng | en |
| dc.contributor.author | 鄭佳安 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:54:25Z | - |
| dc.date.available | 2015-08-19 | |
| dc.date.copyright | 2012-08-19 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-13 | |
| dc.identifier.citation | [1] B. Razavi, “Design of Analog CMOS Integrated Circuits,” 1st Ed., McGraw-Hill, 2001.
[2] J. Cao et al., “OC-192 Receiver in Standard 0.18-μm CMOS,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 187-188, Feb. 2002. [3] B. Razavi, 'Design of Integrated Circuits for Optical Communications,” 1st Ed., Mc-Graw Hill, 2003. [4] J. C. Scheytt, G. Hanke and U. Langmann, “A 0.155, 0.622, and 2.488 Gb/s Automatic Bit Rate Selecting Clock and Data Recovery IC for Bit Rate Transparent SDH Systems,” in IEEE Intl. Solid-State Circuit Conf. Dig. Tech. Paper, pp. 348-349, Feb. 1999. [5] P. Trischitta and E. Varma, “Jitter in Digital Transmission Systems,” Norwood, MA: Artech House, 1989. [6] C. Hogge, “A self-correcting clock recovery circuit,” IEEE Journal of Lightwave Technology, vol. LT-3, pp 1312-1314, Dec. 1985. [7] J. D .H. Alexander, “Clock Recovery from Random Binary Data,” Electronics Letters, vol. 11, pp. 541-542, Oct. 1975. [8] J. Lee, Kenneth S. Kundert and B. Razavi, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sept. 2004. [9] R.Kreienkamp, U. Langmann, C. Zimmermann, T. Aoyama, and H. Siedhoff, 'A 10-Gb/s CMOS Clock and Data Recovery Circuit with an Analog Phase Interpolator,' IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 736-743, Mar. 2005. [10] M. Nogawa, K. Nishimura, S Kimura, T. Yoshida, T. Kawamura, M. Togashi, K. Kumozaki, and Y. Ohtomo, ' A 10Gb/s burst-mode CDRIC in 0.13um CMOS,' IEEE International Solid-State Circuits Conference, Feb. 2005. [11] A. Ptttbacker, U. Langmann, and H.-U. Schreiber, 'A Si Bipolar Phase and Frequency Detector IC for Clock Extraction Up to 8 Gb/s,' IEEE Journal of Solid-State Circuits, vol. 27, no. 12, pp. 1747-1751, Dec. 1992. [12] C. -F. Liang, S. -C. Hwu, and S. -I Liu, 'A Jitter-Tolerance-Enhanced CDR Using a GDCO-Based Phase Detector,' IEEE J. Solid-State Circuits, vol. 43, no.5, pp. 1217-1225, May 2008. [13] T. Lee and J. Bulzacchelli, “A 115-MHz clock recovery delay-and phase-locked loop,” IEEE J. Solid-State Circuits, vol. 27, no.12, pp. 1736-1746, Dec. 1992. [14] J. Kim and D.-K Jeong, 'Multi-Gigabit-Rate Clock and Data Recovery Based on Blind Oversampling,' IEEE Communication Magazine, pp. 68-74, Dec. 2003. [15] M. van Ierssel, A. Sheikholeslami, H. Tamura, and W. W. Walker, “A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance,” IEEE J.Solid-State Circuits, vol. 42, no. 10, pp. 2224–2234, Oct. 2007. [16] P. Sang-Hune, C. Kwang-Hee Choi, S. Jung-Bum, S.Jae-Yoon, and P. Hong-June Walker, “A Single-Data-Bit Blind Oversampling Data-Recovery Circuit With an Add-Drop FIFO for USB2.0 High-Speed Interface,” IEEE Trans. on Circuits and Systems, vol. 55, no. 2, pp. 156–160, Feb. 2008. [17] J Lee, K. -S. Kundert, and B. Razavi,' Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits,” IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1571-1580, Sep. 2004. [18] R. C. Walker, “Designing Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems.” [19] B. Sangjin, L. Jyung Chan, S. Jae Hoon, K. Kwangjoon, and Y. Hyun-Kyu, “A 10-Gb/s CMOS CDR and DEMUX IC With a Quarter-Rate Linear Phase Detector,”IEEE J.Solid-State Circuits, vol. 41, no. 11, pp. 2566–257, Nov. 2006. [20] C. Yang, R. Farjad-Rad and M. Horowitz, “A 0.5um CMOS 4.0Gbit/s serial link transeciver with data recovery using oversampling,” IEEE J.Solid-State Circuits, vol. 33, no. 5, pp. 713–722, May 1998. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64557 | - |
| dc.description.abstract | 近年來，由於有線通訊應用的快速成長，在計算機與網路系統中為了增加晶片間的頻寬，高速的I/O時常被使用。其中接收端內的時脈與資料回復電路(CDR)主要用來重建並還原傳輸端所傳送的資料序列。傳統時脈與資料回復電路經常被視為一個負迴授的控制系統，並根據資料序列相位的移動去調整最佳的時脈輸出相位。 然而，另一種CDR架構稱之為'百葉窗式超取樣時脈與資料回復電路'也經常被使用著，此架構在時脈與輸入的關係中不具有相位追隨的能力。 這兩種架構在抖動容忍度的特性上，不同的抖動頻率區間擁有優點和缺點。基於這樣的論點，我們結合兩種不同架構的時脈與資料回復電路和搭配頻寬切換的機制已達到抖動容忍度的改善，特別是在抖動頻率小於迴路頻寬的區間。
在本論文中，一個可程式化頻寬之三倍超取樣混合式時脈與資料回復電路被提出，其中已回復的資料抖動峰對峰值為99.15UI(88.13ps) @4.5Gb/s。在輸入資料速率為4.5Gb/s 和 PRBS length = 10的條件下，抖動容忍度為 1.2UI@10MHz, 5.5UI@1MHz, 和 35UI@100kHz. 供應電壓為1.1V時，電路總消耗功率為46.2mW，總面積為0.98mm2，使用的技術為 UMC 55nm CMOS製程。 | zh_TW |
| dc.description.abstract | In recent years, applications of wirelan communication have been growing rapidly. Meanwhile, high-speed I/O is used to increase the bandwidth between chips in a computer or network. The clock and data recovery (CDR) circuit is responsible for reconstructing the original transmitter bit-stream at the receiver. The CDR has been viewed as a feedback control system that adjusts its output clock according to the phase movement of the input data in the conventional phase-tracking architecture. However, there is another structure of CDR, blind-oversampling based CDR. This CDR is a feed-forward architecture and thus has no phase-tracking between clock and input data. These two types of CDR have their advantages and disadvantages in jitter tolerance performance with different jitter frequency regions. Based on the point at this issue, we combine these two types of CDR and use the programmable bandwidth to enhance the performance jitter tolerance. So the jitter tolerance will be boosted especially in the jitter frequency regions which are below the loop bandwidth.
In our thesis, the 3x-oversampling hybrid clock and data recovery circuit with programmable bandwidth is proposed. The measured peak-to-peak jitter of recovered clock is 99.15mU (88.13ps) and the measured jitter tolerance results are 1.2UI@10MHz, 5.5UI@1MHz, and 35UI@100kHz with 4.5Gb/s data rate and PRBS length = 10, respectively. The power consumption is 46.2mW with 1.1V supply voltage. The total area of chip is 0.98mm2 and this chip is fabricated in the UMC 55nm CMOS technology. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:54:25Z (GMT). No. of bitstreams: 1 ntu-101-R97943021-1.pdf: 8278387 bytes, checksum: f6f6a6436d8b7762c9c176867269d146 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 誌謝 VII
摘要 i Abstract ii Contents iii List of Figures vii List of Tables xi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 Introduction of Clock and Data Recovery Circuit 3 2.1 Introduction 3 2.2 Basic concept of CDR 4 2.2.1 Properties of Binary Random Data 4 2.2.2 Jitter transfer 5 2.2.3 Jitter tolerance 6 2.2.4 Jitter generation 7 2.2.5 Eye diagram 7 2.3 Phase Detector of CDR 9 2.3.1 Hogge phase detector 9 2.3.2 Alexander phase detector 11 2.4 Topologies of CDR circuit 14 2.4.1 PLL based CDR with reference clock 15 2.4.2 Phase Interpolator based CDR 16 2.4.3 Gated Oscillator based CDR 17 2.5 Summary 19 Chapter 3 A Hybrid Clock and Data Recovery Programmable Bandwidth 21 3.1 Introduction 21 3.2 Conventional phase-tracking CDR 22 3.3 Blind-oversampling CDR 28 3.4 Proposed Hybrid CDR 36 3.5 Phase-tracking Loop Circuit Details 44 3.5.1 Quarter-rate Phase Detector 45 3.5.2 Programmable Charge Pump 50 3.5.3 Voltage-controlled Oscillator 53 3.5.4 12-Phase Generator 57 3.6 Oversampling Loop Circuit Details 61 3.6.1 Data Sampler circuit 63 3.6.2 Retimer & XOR array circuit 64 3.6.3 Decision logic & MUX array circuit 66 3.6.4 Data size detector & Data rearrangement circuit 69 3.6.5 FIFO cell array & FIFO address generator circuit 73 3.7 Simulation results 82 3.8 Summary 88 Chapter 4 Experimental Results 91 4.1 Introduction 91 4.2 Print Circuit Board Design 91 4.3 Measurement Setup 93 4.4 Measurement results 95 4.5 Summary 101 Chapter 5 Conclusions and Future Works 103 5.1 Conclusions 103 5.2 Future Works 103 Bibliography 105 Biography 108 | |
| dc.language.iso | en | |
| dc.subject | 時脈與資料回復電路 | zh_TW |
| dc.subject | CDR | zh_TW |
| dc.subject | 混合式CDR | zh_TW |
| dc.subject | 超取樣CDR | zh_TW |
| dc.subject | 抖動容忍度 | zh_TW |
| dc.subject | Clock and data recovery | en |
| dc.subject | CDR | en |
| dc.subject | Hybrid CDR | en |
| dc.subject | Oversampling CDR | en |
| dc.subject | Jitter tolerance | en |
| dc.title | 可程式化頻寬之三倍超取樣混合式時脈與資料回復電路 | zh_TW |
| dc.title | A 3x-Oversampling Hybrid Clock and Data Recovery Circuit with Programmable Bandwidth | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵,曹恆偉,陳巍仁 | |
| dc.subject.keyword | 時脈與資料回復電路,CDR,混合式CDR,超取樣CDR,抖動容忍度, | zh_TW |
| dc.subject.keyword | Clock and data recovery,CDR,Hybrid CDR,Oversampling CDR,Jitter tolerance, | en |
| dc.relation.page | 109 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-13 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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