請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64498
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊佳玲(Chia-Lin Yang) | |
dc.contributor.author | Min-Zhong Lu | en |
dc.contributor.author | 呂敏中 | zh_TW |
dc.date.accessioned | 2021-06-16T17:50:47Z | - |
dc.date.available | 2013-08-18 | |
dc.date.copyright | 2012-08-18 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-13 | |
dc.identifier.citation | [1] C. Lefurgy, K. Rajamani, F. Rawson, W. Felter, M. Kistler, and T. W. Keller, “Energy Management for Commercial Servers,” IEEE Computer, vol. 36, no. 12, pp. 39–48, Dec. 2003.
[2] S. Schechter, G. Loh, K. Strauss, and D. Burger, “Use ECP, not ECC, for Hard Failures in Memories,” in Proceeding of International Symposium on Computer Architecture, 2010. [3] D. Li, J. S. Vetter, G. Marin, C. McCurdy, C. Cira, Z. Liu, andW. Yu, “Identifying Opportunities for Byte-Addressable Non-Volatile Memory in Extreme-Scale Scientific Applications,” in Proceeding of International Parallel and Distributed Processing Symposium, 2012. [4] C. Lam, “Cell Design Considerations for Phase Change Memory as a Universal Memory,” in Proceeding of International Symposium on VLSI Technology, Systems and Applications, 2008. [5] B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, “Architecting Phase Change Memory as a Scalable DRAM Alternative,” in Proceeding of International Symposium of Computer Architecture, 2009. [6] P. Zhou, B. Zhou, J. Yang, and Y. Zhang, “A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology,” in Proceeding of International Symposium of Computer Architecture, 2009. [7] D. Narayanan and O. Hodson, “Whole-System Persistence,” in Proceeding of International Conference on Architectural Support for Programming Languages and Operating Systems, 2012. [8] M. K. Qureshi, V. Srinivasan, and J. A. Rivers, “Scalable High Performance Main Memory System Using Phase-Change Memory Technology,” in Proceeding of International Symposium on Computer Architecture, 2009. [9] ITRS. (2011) Process Integration, Devices, and Structures. [Online]. Available: http://www.itrs.net/ [10] I. Song, M.-H. Park, H. Chung, S. Chang, B. Cho, J. Kim, Y. Oh, D. Kwon, J. Sunwoo, J. Shin, Y. Rho, C. Lee, M. G. Kang, J. Lee, Y. Kwon, S. Kim, J. Kim, Y.-J. Lee, Q.Wang, S. Cha, S. Ahn, H. Horii, J. Lee, K. Kim, H. Joo, K. Lee, Y.-T. Lee, J. Yoo, and G. Jeong, “A 20nm 1.8V 8Gb PRAM with 40MB/s Program Bandwidth,” in Proceeding of International Solid-State Circuits Conference, 2012. [11] T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M.-H. Lee, A. Schrott, M. Yang, B. Breitwisch, C.-F. Chen, E. Joseph, M. Lamorey, R. Cheek, S.-H. Chen, S. Zaidi, S. Raoux, Y. Chen, Y. Zhu, R. Bergmann, H.-L. Lung, and C. Lam, “Write Strategies for 2 and 4-bit Multi-Level Phase-Change Memory,” in Proceeding of International Electron Devices Meeting, 2007. [12] A. L. Lacaita and D. Mantegazza, “Recovery and Drift Dynamics of Resistance and Threshold Voltages in Phase-Change Memories,” IEEE Transactions on Electron Devices, vol. 54, no. 2, pp. 308–315, Feb. 2007. [13] M. K. Qureshi, F. M. Franceschini, and L. A. Lastras-Montano, “Improving Read Performance of Phase Change Memories via Write Cancellation and Write Pausing,” in Proceeding of International Symposium on High Performance Computer Architecture, 2010. [14] B.-D. Yang, J.-E. Lee, J.-S. Kim, J. Cho, S.-Y. Lee, and B.-G. Yu, “A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme,” in Proceeding of International Symposium on Circuits and Systems, 2007. [15] A. Hay, K. Strauss, T. Sherwood, G. H. Loh, and D. Burger, “Preventing PCM Banks from Seizing Too Much Power,” in Proceeding of International Symposium on Microarchitecture, 2011. [16] G. Dhiman, R. Ayoub, and T. Rosing, “PDRAM: A Hybrid PRAM and DRAM Main Memory System,” in Proceeding of Design Automation Conference, 2009. [17] Y. Kim, S. Yoo, and S. Lee, “Write Performance Improvement by Hiding R Drift Latency in Phase-Change RAM,” in Proceeding of Design Automation Conference, 2012. [18] M. Qureshi, M. Franceschini, A. Jagmohan, and L. Lastras, “PreSET: Improving Read-Write Performance of Phase Change Memories by Exploiting Asymmetry inWrite Times,” in Proceeding of International Symposium on Computer Architecture, 2012. [19] M. K. Qureshi, J. Karidis, M. Franceschini, V. Srinivasan, L. Lastras, and B. Abali, “Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling,” in Proceeding of International Symposium on Microarchitecture, 2009. [20] N. H. Seong, D. H. Woo, V. Srinivasan, J. A. Rivers, and H.-H. S. Lee, “SAFER: Stuck-At-Fault Error Recovery for Memories,” in Proceeding of International Symposium on Microarchitecture, 2010. [21] D. H. Yoon, N. Muralimanohar, J. Chang, P. Ranganathan, N. P. Jouppi, and M. Erez, “FREE-p: Protecting Non-Volatile Memory against both Hard and Soft Errors,” in Proceeding of International Symposium on High Performance Computer Architecture, 2011. [22] S. Cho and H. Lee, “Flip-N-Write: A Simple Deterministic Technique to Improve PRAM Write Performance, Energy and Endurance,” in Proceeding of International Symposium on Microarchitecture, 2009. [23] B. Jacob, S. W. Ng, and D. T. Wang, Memory Systems: Cache, DRAM, Disk. Morgan Kaufmann Publishers, 2008. [24] S. Rixner, W. J. Dally, U. J. Kapasi, P. Mattson, and J. D. Owens, “Memory Access Scheduling,” in Proceeding of International Symposium of Computer Architecture, 2000. [25] P. Zhou, Y. Du, Y. Zhang, and J. Yang, “Fine-Grained QoS Scheduling for PCM-based Main Memory Systems,” in Proceeding of International Symposium on Parallel and Distributed Processing, 2010. [26] H. Zheng, J. Lin, Z. Zhang, E. Gorbatov, H. David, and Z. Zhu, “Mini-rank: Adaptive DRAM Architecture for Improving Memory Power Efficiency,” in Proceeding of International Symposium on Microarchitecture, 2008. [27] JEDEC. (2011) Low Power Double Data Rate 2 (LPDDR2) Standard: JESD209-2E. [Online]. Available: http://www.jedec.org/ [28] S. Park, D. Jung, J. Kang, J. Kim, and J. Lee, “CFLRU: A Replacement Algorithm for Flash Memory,” in Proceeding of International Conference on Compilers Architecture and Synthesis for Embedded Systems, 2006. [29] H.-H. S. Lee, G. S. Tyson, and M. K. Farrens, “EagerWriteback - a Technique for Improving Bandwidth Utilization,” in Proceeding of International Symposium on Microarchitecture, 2000. [30] A. Patel, F. Afram, S. Chen, and K. Ghose, “MARSSx86: A Full System Simulator for x86 CPUs,” in Proceeding of Design Automation Conference, 2011. [31] P. Rosenfeld, E. Cooper-Balis, and B. Jacob, “DRAMSim2: A Cycle Accurate Memory System Simulator,” IEEE Computer Architecture Letters, vol. 10, no. 1, pp. 16–19, 2011. [32] Micron. (2009) 4Gb DDR3 SDRAM component data sheet: MT41J256M16. [Online]. Available: http://www.micron.com/ [33] J. L. Henning, “SPEC CPU2006 benchmark descriptions,” SIGARCH Computer Architecture News, vol. 34, no. 4, pp. 1–17, Sept. 2006. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64498 | - |
dc.description.abstract | 隨著摩爾定律( Moore’s Law )繼續成立,可同時執行的應用程式的數量持續增長,對主記憶體的容量需求也繼續增加當中。近年來,學者們致力於研究能比動態隨機存取記憶體( DRAM )提供更大容量、更低耗電的記憶體技術。其中,具有非揮發性及極佳的製程微縮性的相變化記憶體( PCM,phase-change memory )被視為是取代DRAM 的最佳候選。然而,相變化記憶體仍存在一些需被克服的缺點。例如,它的寫入速度比起動態隨機存取記憶體慢得許多,進而成為相變化主記憶體系統的效能障礙。
在本篇論文,我延伸前一文獻所提出,已證實可彌補相變化記憶體之較差效能之「多項目窄列緩衝區相變化記憶體組織」( multiple narrow row buffer organization for PCM )。我提出兩個「列緩衝區管理策略」( row buffer management policy ),及兩個「記憶體庫間平行存取方案」( intra-bank parallelism scheme )來更加利用多項目窄列緩衝區之效能潛力。實驗模擬顯示列緩衝區管理策略對於記憶體密集之工作負載具有平均2.27% 及最大2.51% 之系統效能提昇,而記憶體庫間平行存取方案對於記憶體密集之工作負載具有最大67.5% 之系統效能提昇。另外,記憶體庫間平行存取方案對於較不記憶體密集之工作負載亦有最大12%的系統效能提昇。 | zh_TW |
dc.description.abstract | As Moore’s Law continues to hold true, the number of concurrently running applications has been increasing, and the capacity requirement of main memory has been much aggravated. For recent years, researchers have been studying new memory technologies that are envisioned to provide more memory capacity and lower power than the conventional DRAM. Among them, phase-change memory (PCM) has been considered as the best candidate to replace DRAM as main memory due to its non-volatility, byte-addressability, and superior scalability. Nevertheless, there have still been a number of drawbacks of PCM that need to be addressed in order to enjoy the full benefit of it. For example, the write latency of PCM is much longer than that of DRAM, which often poses as a performance bottleneck for PCM-based main memory system.
In this thesis, I extend one previous work that proposed the multiple narrow row buffer organization for PCM, which was reported to be effective in mitigating the relatively poor performance of PCM; I propose two row buffer management policies and two intra-bank parallelism schemes to exploit the full potential of such organization. Simulation shows that the proposed row buffer management policies bring an average of 2.27% and a maximum of 2.51% performance improvement, and that the proposed intra-bank parallelism schemes bring a maximum of additional 67.5% performance improvement for memory intensive workloads. Moreover, intra-bank parallelism schemes are observed to provide a maximum of 12% performance improvement for less memory intensive workloads. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:50:47Z (GMT). No. of bitstreams: 1 ntu-101-R98922050-1.pdf: 7761378 bytes, checksum: 93d4ca787ede8e3c8c234c6d20b01a67 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | Acknowledgments i
摘要 ii Abstract iii 1 Introduction 1 2 Background and Related Works 4 2.1 Phase-Change Memory . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.2 Memory Structures and Accesses . . . . . . . . . . . . . . . . . . . . 6 2.3 Multiple Row Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Mechanisms 11 3.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . . . . . 11 3.1.1 Clean-First Least-Recently Used (CFLRU) row buffer replacement policy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1.2 Early Write-Back (EWB) . . . . . . . . . . . . . . . . . . . . . 13 3.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . . . . . 14 3.2.1 Concurrent Row Buffer Accesses (CRB) . . . . . . . . . . . . 14 3.2.2 Concurrent Data Sensing and Programming (CSP) . . . . . . 17 4 Experimental Methodology 20 5 Experimental Results 23 5.1 High-MPKIWorkload Mixes . . . . . . . . . . . . . . . . . . . . . . 23 5.1.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . 24 5.1.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . 26 5.2 Medium- and Low-MPKI Workload Mixes . . . . . . . . . . . . . . 32 5.2.1 Row Buffer Management Policies . . . . . . . . . . . . . . . . 32 5.2.2 Intra-Bank Parallelism Schemes . . . . . . . . . . . . . . . . . 36 6 Conclusions 41 Bibliography 43 | |
dc.language.iso | en | |
dc.title | 相變化主記憶體之列緩衝區管理策略 | zh_TW |
dc.title | Row Buffer Management Policies in PCM Main Memory Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 徐慰中(Wei-Chung Hsu),蘇雅韻(Ya-Yunn Su),王成淵(Cheng-Yuan Michael Wang) | |
dc.subject.keyword | 相變化記憶體,主記憶體架構, | zh_TW |
dc.subject.keyword | Phase-change memories,main memory architecture, | en |
dc.relation.page | 46 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 7.58 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。