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標題: | 降低突波與動態敏感性之鎖相迴路分析與設計 Analysis and Design of Phase-Locked Loops for Reducing Spur and Dynamic Sensitivity |
作者: | Yu-Cheng Chen 陳佑政 |
指導教授: | 張帆人 |
關鍵字: | 抖動峰值,迴路延遲,線性矩陣不等式,迴路頻寬,鎖相迴路,參考突波,製程、電壓以及溫度的變異,z-域, Jitter peaking,Loop delay,Linear matrix inequality (LMI),Loop bandwidth,Phase-locked loop (PLL),Reference spur,PVT variation,z-domain, |
出版年 : | 2012 |
學位: | 博士 |
摘要: | 除了相位雜訊之外,鎖相迴路的輸出訊號包含了突波(spurs)。這兩種不同類型的雜訊影響了輸出訊號的頻譜純淨度。在無線接收機中,突波對於訊號雜訊比的影響是一個棘手的問題。降低迴路頻寬來抑制突波是最直接的方式,然而這會影響到輸出訊號的相位雜訊特性。另一個直接的方式為降低電壓控制震盪器的增益,但這會限制電壓控制震盪器的操作範圍。
本論文係以控制理論為基礎,提出濾波器參數的調整方法來達成突波抑制。考慮了迴路延遲,本論文在z-域來處理濾波器的設計問題,提出以線性矩陣不等式為基礎的設計方法來抑制突波,並且不需要降低迴路頻寬。這個方法適用於三階與四階鎖相迴路的設計。與常見的濾波器設計方法比較,我們的方法能提供更大的突波抑制。 迴路頻寬與抖動峰值(稱為動態參數)的選擇影響了鎖相迴路的性能表現。譬如,頻寬內相位雜訊(in-band phase noise)與頻寬外相位雜訊(out-of-band phase noise)的取捨由迴路頻寬決定。另外,抖動峰值決定迴路穩定度等等。由於製程、電壓以及溫度的變異(PVT variation),迴路濾波器的被動元件、電壓控制震盪器的增益以及電荷幫浦電流的實際值會不同於設計值。因此,實際的動態參數也會不同於設計值,這影響了鎖相迴路的性能表現。 基於z-域的鎖相迴路等效模型,本論文提出一個分析方法,探討迴路濾波器極點的選擇對於動態參數變異的影響。根據分析結果,我們提出了一個濾波器設計策略。當需要大的相位邊限以及動態參數變異主要由電阻變異所影響時,與常見的濾波器設計方法比較,此設計策略不但能降低PVT變異對於動態參數的影響,還能獲得更佳的突波性能。 In addition to the phase noise, the output signal of a phase-locked loop (PLL) includes the unwanted spur. The spectral purity of the output signal is determined by the two types of noise. In wireless communication receivers, the spur is a troublesome problem, affecting the signal to noise ratio. The easiest approach to improving the spur performance is to reduce the loop bandwidth. However, this solution affects the phase noise characteristic of the output signal. Another straightforward solution is to decrease the gain of the voltage-controlled oscillator (VCO). The drawback is that this solution limits the operation range of the VCO. This dissertation presents a loop filter design method to achieve the spur reduction without having to decreasing the loop bandwidth, while considering the loop delay effects. Using control system theory, the dissertation solves the loop filter design problem in the z-domain and proposes an LMI-based method for the spur reduction. This method is applicable to both the third- and fourth-order charge-pump phase-locked loops. Compared to the conventional methods, the proposed method offers greater spur reduction without altering the loop bandwidth. The performances of PLLs mainly depend on the dynamic parameters: the loop bandwidth and the jitter peaking. For example, the loop bandwidth plays an important role in trade-off between the in-band phase noise and the out-of-band phase noise. The jitter peaking directly affects the loop stability. Due to process, voltage, and temperature (PVT) variations, the actual values of the passive components, the VCO gain and the charge-pump current will differ from their designed values. Therefore, the actual dynamic parameters are rarely equal to their well-designed values. This affects the performances of the system. Using a z-domain PLL model, this dissertation presents an analysis method to explore the effects of the loop filter pole on the dynamic parameter changes. Based on the results of the analysis, we propose a design strategy. Compared to the conventional method, this strategy would lessen the effects of the PVT variation on the dynamic parameter and improve the spur performance when the dynamic parameter changes are dominated by the resistor and large phase margin is required. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64219 |
全文授權: | 有償授權 |
顯示於系所單位: | 電機工程學系 |
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