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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 陳中平(Chung-Ping Chen) | |
dc.contributor.author | Chi-Ping Lin | en |
dc.contributor.author | 林其平 | zh_TW |
dc.date.accessioned | 2021-06-16T17:34:57Z | - |
dc.date.available | 2012-08-19 | |
dc.date.copyright | 2012-08-19 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-14 | |
dc.identifier.citation | [1] L. F. Ding, ' Algorithm and architecture design of prediction core for stereo video coding systems,' M.S. thesis, Nation Taiwan University, Taipei, ON, Taiwan, 2005.
[2] L. Bickford, 'The EyeCare Reports,' 1995, http://www.eyecarecontacts.com/Dr._Larry_Bickford/Home.html [3] Y. H. Ching and Y. P. Huang, “Development and Researches of Real 3D Display Technologies,” 光學工程, vol. 98, pp.1-8, June 2007 [4] G. D. Diao, ” 3D Display and Application,” Electronics and Optoelectronics Research Laboratories, Industrial Technology Research Institute, Taiwan, Tech. Rep.,2010. [5] M. T. M. Lambooij, W. A. IJsselsteij, and I. Heynderickx,” Visual Discomfort in Stereoscopic Displays: A Review,” SPIE-IS&T, vol. 6490, pp. 1-13, 2007 [6] M. T. M. Lambooij and W. A. IJsselsteij, “Visual Discomfort and Visual Fatigue of Stereoscopic Displays: A Review,” J. Imaging Sci. Technol., 53, pp. 1-14, May 2009 [7] A. Woods, T. Docherty, and R. Koch, ”Image Distortions in Stereoscopic Video Systems,” Stereoscopic Displays and Applications IV, Proc. SPIE vol. 1915, pp. 1-13, Feb. 1993. [8] V. M. Dwyer, S. Agha, and V. A. Chouliaras, ”Reduced-Bit Full Search Block-Matching Algorithms and Their Hardware Realizations,” Advanced Concepts for Intelligent Vision Systems, pp. 372-380, 2005. [9] T. Y. Wu, “Automation of Disparity Adjustment According to Human Factor for Depth-Image-Based Rendering,” M.S. thesis, Nation Taiwan University, Taipei, ON, Taiwan, 2012. [10] S. Kimura, T. Shinbo, H. Yamaguchi, E. Kawamura, and K. Nakano,“A convolver-based real-time stereo machine (SAZAN),” in Proc. IEEE Comput. Soc. Conf. Comput. Vision Pattern Recognit., Fort Collins, CO, vol. 1. Jun. 1999, pp. 457–463. [11] A. Darabiha, J. Rose, and W. J. Maclean, “Video-rate stereo depth measurement on programmable hardware,” in Proc. IEEE Comput. Soc. Conf. Comput. Vision Pattern Recognit., Madison, WI, vol. 1. Jun. 2003, pp. 203–210. [12] W. Y. Lee, “Improved Hole-filling Algorithm and Hardware Implementation for Virtual View Generation,” M.S. thesis, Nation Tsing Hua University, Hsinchu, ON, Taiwan, 2011. [13] C. Y. Chun, “Analysis and Hardware Design of Intermediate View Generation Using Adaptive Disparity Estimation Based on Spatial and Temporal Correlation,” M.S. thesis, Nation Tsing Hua University, Hsinchu, ON, Taiwan, 2007. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64209 | - |
dc.description.abstract | 雙眼視覺系統同時間能夠顯示兩張不同的影像讓左右兩眼接收,使得使用者有更為真實的觀感。因此如何提供使用者愉快舒適的觀賞經驗將會變成一個重要的主題。
本篇論文中,我們會先由人因實驗的結果分析視覺疲勞產生的原因。其中深度資訊的感受會對人類的視覺系統產生最大的影響,所以必須被控制在適當的範圍內。接下來,我們利用幾何學的模型來推論三維空間(物件存在空間)與二維空間(影像顯示空間)的轉換。並藉此深入探討來進一步的獲得深度(視差)和相機拍攝參數的關係。我們利用視差估計來搜尋兩張畫面間的深度資訊,並且產生深度圖。然後使用基於深度圖繪圖法同時融合視差與參數的關係來回復調整過後的影像。 為了處理伴隨著立體影像所帶來的大量資料,我們所挑選的現場可程式化邏輯陣列版(消費性電子影像套件)包括大容量的同步動態隨機存取記憶體。另一個目的是為了和高解析度多媒體介面傳輸接軌。因此硬體實現的重點會被放在如何設計架構來配合這兩個問題。我們的硬體架構會透過高解析度多媒體介面傳輸來展現出演算法的結果,同時也代表了對於同步動態隨機存取記憶體的成功操作。 此系統在可程式化邏輯陣列板上,可以對於1080逐行掃描的視訊顯示格式達到每秒 1.72 張畫面處理。視差搜尋範圍為[-15,+14]。暫存器數目為6,844個。查找表的數目為9,339個。邏輯數目為8,859個。所使用的靜態隨機存取記憶體為 30,000位元。 | zh_TW |
dc.description.abstract | Stereo video can make users sense depth perception by showing two frames to each eye simultaneously. It can give users vivid information about the scene structure. However, to provide a comfortable view experience on 3DTV must become the main topic.
In this thesis, we analyze the visual fatigue reason by the human factor experiments firstly. The depth information will do major impact on the human visual system. It must be controlled in an appropriate range. Secondly, we utilize the geometry model to obtain the transformation between 3D (object space) and 2D (screen space). Besides, the relation between depth (parallax) and camera parameters was revealed by going deep into the model. We use Disparity Estimation (DE) to search the difference among the two frames. It will export disparity maps for frames rendering. Then, Depth Image Base Rendering (DIBR) which merged the relation is used to reconstruct the modified frames. In order to process the stereo video with the huge amounts of data, the FPGA boards (CVK) we chose includes SDRAMs which are with large capacity. Another reason is to suit the HDMI standard transmission. The point of hardware implementation is the architecture design for the two reasons. The architecture of our system can display algorithm result through HDMI signal. It also represent the SDRAMs are successfully accessed. The system on FPGA board can achieve 1.72 frames per second (fps) in 1080p display format, with DE search range of [-15,+14] in horizontal direction. Registers count is 6.844K. LUTs count is 9.339K. Logic count is 8.859K. The SRAM size is 30K bits. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:34:57Z (GMT). No. of bitstreams: 1 ntu-101-R97943129-1.pdf: 3172214 bytes, checksum: a20cd553551185ff8a1e1bba0895304c (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝 ii 摘要 iii ABSTRACT iv CONTENTS vi LIST OF FIGURES viii LIST OF TABLES x Chapter 1 Introduction 1 1.1 Introduction 1 1.2 Visual Fatigue 1 1.3 The Fundamental of Stereo Vision 2 1.4 The Spartan-6 FPGA Consumer Video Kit 2 1.5 Motivation 3 1.6 Thesis Organization 4 Chapter 2 Overview of Binocular Stereoscopies on 3DTV 5 2.1 Depth Perception (Binocular Depth Cues) 6 2.1.1 Convergence 6 2.1.2 Binocular Disparity (Stereopsis) 7 2.1.3 Horizontal Parallax 7 2.2 Glasses type 3DTV 9 2.3 Causative Factors of Visual Fatigue 11 2.3.1 Excessive binocular disparity 12 2.3.2 Accommodation and convergence mismatch 12 2.3.3 Stereoscopic distortion 14 Chapter 3 Stereo Image Processing System 16 3.1 Stereoscopic Camera and Display System 16 3.2 Stereo Image Processing System 21 3.2.1 Disparity Estimation 22 3.2.2 Disparity Modification and DIBR 24 Chapter 4 Hardware Design for Stereo Image Processing System 25 4.1 Overview of Spartan-6 FPGA Consumer Video Kit 25 4.2 Overview of Hardware Architecture 27 4.3 HDMI Video Interface 29 4.4 The link between Engine and HDMI Video Interface 35 4.5 Architecture of Stereo Image Processing Engine 37 4.5.1 The Memory Access of Disparity Estimation Core 41 4.5.2 The Memory Access of DIBR Core 44 4.5.3 Memory Controller 47 Chapter 5 FPGA Implementation and Experimental Results 48 5.1 The simulation result 49 5.2 The hardware implementation result 52 5.2.1 The implementation result 52 5.2.2 The hardware operation flow 52 5.2.3 The environment of CVK 55 Chapter 6 Conclusion 56 Bibliography 57 | |
dc.language.iso | en | |
dc.title | 增強人眼觀賞舒適度之三維影像優化高速硬體實現-以可現場程式化邏輯為基礎 | zh_TW |
dc.title | High Speed FPGA-based Hardware Implementation of 3D Video Optimization for Human Visual Comfort Enhancement | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 傅楸善,洪士灝 | |
dc.subject.keyword | 立體三維,雙眼視差,視差估計,深度圖繪圖法,可程式化邏輯陣列,同步動態隨機存取記憶體,高解析度多媒體介面, | zh_TW |
dc.subject.keyword | Stereo and 3D,binocular parallax,disparity estimation,depth image base rendering (DIBR),FPGA,SDRAM,HDMI, | en |
dc.relation.page | 58 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-15 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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