請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64014
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王暉(Huei Wang) | |
dc.contributor.author | Yuan-Hung Hsiao | en |
dc.contributor.author | 蕭元鴻 | zh_TW |
dc.date.accessioned | 2021-06-16T17:26:34Z | - |
dc.date.available | 2014-12-10 | |
dc.date.copyright | 2012-12-10 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-16 | |
dc.identifier.citation | [1] S. Pinel, S. Sarkar, P. Sen, B. Perumana, D. Yeh, D. Dawn, and J. Laskar, “A 90-nm
CMOS 60 GHz radio,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 130–601, Feb. 2008. [2] M. Tanomura, Y. Hamada, S. Kishimoto, M. Ito, N. Orihashi, K. Maruhashi, and H. Shimawaki, “TX and RX front-ends for 60 GHz band in 90-nm standard bulk CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 558–635, Feb. 2008. [3] K. Okada, K. Matsushita, K. Bunsen, R. Murakami, A. Musa, T. Sato, H. Asada, N. Takayama, N. Li, S. Ito, W. Chaivipas, R. Minami, and A. Matsuzawa, “A 60 GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 160–162, Feb. 2011. [4] V. Vidojkovic, G. Mangraviti, K. Khalaf, V. Szortyka, K. Vaesen, W. Van Thillo, B. Parvais, M. Libois, S. Thijs, J. Long, C. Soens, and P. Wambacq, “A low-power 57-to-66 GHz transceiver in 40nm LP CMOS with -17db evm at 7gb/s,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 268– 270, Feb. 2012. [5] J.-W. Lai and A. Valdes-Garcia, “A 1 V 17.9 dBm 60 GHz power amplifier in stan- dard 65 nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 424–425, Feb. 2010. [6] C. Law and A.-V. Pham, “A high-gain 60 GHz power amplifier with 20 dBm out- put power in 90 nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 426–427, Feb. 2010. [7] J. Chen and A. Niknejad, “A compact 1 V 18.6 dBm 60 GHz power amplifier in 65 nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Tech- nical Papers (ISSCC), pp. 432–433, Feb. 2011. [8] J. Liu, R. Berenguer, and M. Chang, “Millimeter-wave self-healing power amplifier with adaptive amplitude and phase linearization in 65-nm CMOS,” IEEE Transac- tions on Microwave Theory and Techniques, vol. 60, pp. 1342–1352, May 2012. [9] W. Chan and J. Long, “A 58-65 GHz neutralized CMOS power amplifier with PAE above 10 % at 1-V supply,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 554– 564, March 2010. [10] Y. Yu, P. Baltus, A. de Graauw, E. van der Heijden, C. Vaucher, and A. van Roer- mund, “A 60 GHz phase shifter integrated with LNA and PA in 65 nm CMOS for phased array systems,” IEEE Journal of Solid-State Circuits, vol. 45, pp. 1697–1709, Sept. 2010. [11] K.-Y. Wang, T.-Y. Chang, and C.-K. Wang, “A 1 V 19.3 dBm 79 GHz power ampli- fier in 65nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 260–262, Feb. 2012. [12] Q. Gu, Z. Xu, and M.-C. Chang, “Two-way current-combining W-band power am- plifier in 65-nm CMOS,” IEEE Transactions on Microwave Theory and Techniques, vol. 60, pp. 1365–1374, May 2012. [13] M. Chang and G. Rebeiz, “A wideband high-efficiency 79-97 GHz SiGe linear power amplifier with >90 mW output,” in IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 69–72, Oct. 2008. [14] Y.-S. Jiang, J.-H. Tsai, and H. Wang, “A W-band medium power amplifier in 90 nm CMOS,” IEEE Microwave and Wireless Components Letters, vol. 18, pp. 818–820, Dec. 2008. [15] A. Komijani and A. Hajimiri, “A wideband 77-GHz, 17.5-dBm fully integrated power amplifier in silicon,” IEEE Journal of Solid-State Circuits, vol. 41, pp. 1749– 1756, Aug. 2006. [16] D. Sandstrom, M. Varonen, M. Karkkainen, and K. Halonen, “W-band CMOS am- plifiers achieving 10 dBm saturated output power and 7.5 dB NF,” IEEE Journal of Solid-State Circuits, vol. 44, pp. 3403–3409, Dec. 2009. [17] N. Kurita and H. Kondoh, “60 GHz and 80 GHz wide band power amplifier MMICs in 90nm CMOS technology,” in IEEE Radio Frequency Integrated Circuits Sympo- sium, pp. 39 –42, June 2009. [18] Y. Hamada, M. Tanomura, M. Ito, and K. Maruhashi, “A high gain 77 GHz power amplifier operating at 0.7 V based on 90 nm CMOS technology,” IEEE Microwave and Wireless Components Letters,, vol. 19, pp. 329–331, May 2009. [19] R. Ben Yishay, R. Carmon, O. Katz, and D. Elad, “A high gain wideband 77 GHz SiGe power amplifier,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 529–532, May 2010. [20] D. Chan and M. Feng, “A compact W-band CMOS power amplifier with gain boost- ing and short-circuited stub matching for high power and high efficiency operation,” IEEE Microwave and Wireless Components Letters, vol. 21, pp. 98–100, Feb. 2011. [21] D. Sandstrom, B. Martineau, M. Varonen, M. Karkkainen, A. Cathelin, and K. Halo- nen, “94 GHz power-combining power amplifier with +13 dBm saturated output power in 65nm CMOS,” in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 1–4, June 2011. [22] V. Giammello, E. Ragonese, and G. Palmisano, “A 15-dBm SiGe BiCMOS PA for 77-GHz automotive radar,” IEEE Transactions on Microwave Theory and Tech- niques, vol. 59, pp. 2910–2918, Nov. 2011. [23] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design. Coral Gables, Florida: Prentic-Hall, Inc., second ed., 1997. [24] S. C. Cripps, RF Power Amplifier for Wireless Comunications. Norwood, MA: Artech House, second ed., 1999. [25] L. Samoska, K.-Y. Lin, H. Wang, Y.-H. Chung, M. Aust, S. Weinreb, and D. Dawson, “On the stability of millimeter-wave power amplifiers,” in IEEE MTT-S International Microwave Symposium Digest, vol. 1, pp. 429–432, 2002. [26] R. Freitag, “A unified analysis of MMIC power amplifier stability,” in IEEE MTT-S International, pp. 297 –300 vol.1, June 1992. [27] W. Chan, J. Long, M. Spirito, and J. Pekarik, “A 60 GHz-band 1 V 11.5 dBm power amplifier with 11% PAE in 65nm CMOS,” in IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp. 380–381,381a, Feb. 2009. [28] Y.-N. Jen, J.-H. Tsai, T.-W. Huang, and H. Wang, “Design and analysis of a 55-71 GHz compact and broadband distributed active transformer power amplifier in 90 nm CMOS process,” IEEE Transactions on Microwave Theory and Techniques, vol. 57, pp. 1637–1646, July 2009. [29] S. Marsh, “MMIC power splitting and combining techniques,” in IEE Tutorial Col- loquium on Design of RFIC’s and MMIC’s, pp. 6/1–6/7, Nov 1997. [30] S. Marsh, D. Lau, R. Sloan, and L. Davis, “Design and analysis of an X-band mmic ”bus-bar” power combiner,” in Symposium on High Performance Electron Devices for Microwave and Optoelectronic Applications, pp. 164–169, 1999. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/64014 | - |
dc.description.abstract | 在本論文中,我們將以高階的金氧半場效電晶體 (CMOS) 進行毫米波功率放大
器的設計與製作。設計重點分別為降低靜態功率消耗改善低功率操作時的效率, 以及輸出功率的提升。 第一部分是以 90 奈米金氧半場效電晶體低功耗製程設計 V 頻段的功率放大 器,並提出一個由峰值檢測器改良而成的自適性偏壓調整電路,這個功率放大器 總共有兩個版本。在沒有使用自適性偏壓 (adaptive bias) 的電路中,小信號增益為16 dB,輸出飽和功率為 13.8 dBm,最大附加功率效率 (PAE)13.5%。在 1dB 增益壓縮時的輸出功率 (OP 1dB ) 為 10.3 dBm,附加功率效率為 7.3%。而在另外一個版本的電路中,小信號增益為 12.7 dB,輸出飽和功率為 12.3 dBm。1dB 增益壓縮時的輸出功率為 10.7 dBm,附加功率效率則提升至 8.3%。透過自動調整偏壓的方式,當功率放大器為靜態操作時,可以節省 57.6% 的直流功耗。 第二部分是使用 65 奈米金氧半場效電晶體製程設計一個W頻段具有高輸出功 率的功率放大器。我們提出了一種新型的功率結合方式來實現多顆電晶體的功率 結合匹配網路。透過功率結合,這個功率放大器可以達到飽和輸出功率 18.3 dBm 以及在 1dB 增益壓縮時的輸出功率為 17.5 dBm,並有 12.7 dB 的線性增益。此外,為了達到高輸出功率,必須給予電路足夠的直流功耗。在高直流功耗的操作狀態下,電路本身的寄生效應已經變得不可忽略,這些現象也將會一併在論文中探討。 透過本論文得到的成果可以得知,使用金氧半場效電晶體製程設計的毫米波功 率放大器具有相當的競爭力。藉由輸出功率的提升,將能大幅改善金氧半場效電 晶體毫米波系統的效能與傳輸距離,並有助於在高速傳輸與高解析度影像偵測等 系統應用的研發與整合。 | zh_TW |
dc.description.abstract | In this thesis, we will present two power amplifiers using CMOS processes. These designs based on two different criteria, which are quiescent dc power reduction and high
output power delivery. The V-band power amplifier using 90-nm CMOS LP process is designed with the adaptive bias circuit based on envelope detector architecture to control the dc power. Two versions power amplifiers are demonstrated, which are with and without adaptive bias circuit. The measured small signal gain of the PA without adaptive bias is 16 dB. Measured saturation power is 13.8 dBm with peak PAE 13.5% and the OP 1dB is 10.3 dB with PAE 7.3%. In another version, the measured small signal gain of the PA with adaptive bias is 12.7 dB, which saturation power is 12.3 dBm. The OP 1dB is 10.7 dBm with PAE 8.3%. With adaptive bias technique, about 57.6% quiescent dc power consumption can be reduced from 168.6 mW to 72 mW, and the efficiency is also improved in low power operation. The W-wand power amplifier for high output power is presented in 65-nm CMOS process. A design method to realize a large number of transistors combined matching network is proposed to achieve high output power, and several parasitic effects in high dc power operation are also introduced. The power amplifier achieves measured saturation power of 18.3 dBm with peak PAE 9.4%, which OP 1dB is 17.5 dBm and the linear gain is 12.7 dB. To the author’s knowledge, this output power is the highest for CMOS power amplifiers at 94 GHz to date. These results present that CMOS PAs are still competitive at high frequencies, which are beneficial to integrate systems in CMOS for millimter-wave applications such as active imaging systems and high data-rate wireless communications. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:26:34Z (GMT). No. of bitstreams: 1 ntu-101-R99942022-1.pdf: 75831317 bytes, checksum: 0412a1a10bf1e453bbd00a7872d3b0bd (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 誌謝 i
中文摘要 iv ABSTRACT v Contents vi List of Figures viii List of Tables xiv 1 Introduction 1 1.1 Background and Motivation........................................................................ 1 1.2 Literature Survey ........................................................................................ 2 1.2.1 Power Amplifier with Efficiency Improvement............................... 2 1.2.2 W band Power Amplifier with High Output Power ......................... 3 1.3 Contributions.............................................................................................. 4 1.4 Thesis Organization .................................................................................... 4 2 A 60 GHz Power Amplifier with Efficiency Improvement in 90-nm CMOS Low-Power Process 5 2.1 V-band Power Amplifier Design ................................................................. 5 2.1.1 Circuit Design ................................................................................ 5 2.1.2 Chip Layout and Simulation Results............................................... 8 2.1.3 Stability Consideration ................................................................... 11 2.2 Adaptive Bias Technique ............................................................................ 18 vi2.3 Power Amplifier with Adaptive Bias Technique.......................................... 23 2.4 Experimental Results .................................................................................. 33 2.5 Discussions................................................................................................. 40 2.6 Summary .................................................................................................... 45 3 A 94 GHz Power Amplifier with 18.3-dBm Output Power using 65-nm CMOS Process 46 3.1 Design Methodology for Matching Network with Power Combiner/Splitter 46 3.2 DC Bias Consideration ............................................................................... 51 3.2.1 Parasitic Resistance Effect.............................................................. 51 3.2.2 Geometric Limitations of the Layout in Combining Network.......... 70 3.3 Circuit Design............................................................................................. 75 3.3.1 Circuit Structure and Power Budget Plan ........................................ 75 3.3.2 Matching Network Design.............................................................. 76 3.3.3 Layout Consideration and Simulation Results................................. 82 3.3.4 Stability Consideration ................................................................... 84 3.4 Experimental Results and Discussions ........................................................ 88 3.5 Summary .................................................................................................... 94 4 Conclusions 96 References 98 | |
dc.language.iso | en | |
dc.title | 互補式金氧半場效電晶體毫米波頻段功率放大器研製與效率改善之研究 | zh_TW |
dc.title | Research of CMOS Millimeter-Wave Power Amplifier with High Output Power and Efficiency Improvement | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林坤佑(Kun-You Lin),章朝盛(Chau-Ching Chiong),蔡作敏(Zuo-Min Tsai),張鴻埜(Hong-Yeh Chang) | |
dc.subject.keyword | 功率放大器,金氧半場效電晶體,自適性偏壓機制,高輸出功率,毫米波,V 頻段,W 頻段, | zh_TW |
dc.subject.keyword | Power amplifier,CMOS,adaptive bias,high output power,millimeter-wave,V-band,W-band, | en |
dc.relation.page | 101 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 74.05 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。