請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63955
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 楊佳玲(Chia-Lin Yang) | |
dc.contributor.author | Yung-End Hsieh | en |
dc.contributor.author | 謝詠恩 | zh_TW |
dc.date.accessioned | 2021-06-16T17:24:17Z | - |
dc.date.available | 2017-08-28 | |
dc.date.copyright | 2012-08-28 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-16 | |
dc.identifier.citation | Bibliography
[1] G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy. Overview of candidate device technologies for storage-class memory. IBM Journal of Research and Development, 52(4.5):449 {464, july 2008. [2] R. Caceres, F. Douglis, K. Li, and B. Marsh. Operating system implications of solid-state mobile computers. In Workstation Operating Systems, 1993. Pro- ceedings., Fourth Workshop on, pages 21 {27, oct 1993. [3] Y.-C. Chu, C.-T. Chao, P.-C. Chang, S.-C. Chang, J.-C. Wu, and T.-S. Chin. Characteristics of tega sb thin lms for phase-change memory. Magnetics, IEEE Transactions on, 47(3):637 {640, march 2011. [4] J. Condit, E. B. Nightingale, C. Frost, E. Ipek, B. Lee, D. Burger, and D. Co- etzee. Better i/o through byte-addressable, persistent memory. In Proceedings of the ACM SIGOPS 22nd symposium on Operating systems principles, SOSP '09, pages 133{146, New York, NY, USA, 2009. ACM. [5] G. Dhiman, R. Ayoub, and T. Rosing. Pdram: A hybrid pram and dram main memory system. In Design Automation Conference, 2009. DAC '09. 46th ACM/IEEE, pages 664 {669, july 2009. [6] G. Even, Y. Fais, M. Medina, S. M. Shahar, and A. Zadorojniy. Real-time video streaming in multi-hop wireless static ad hoc networks. In Proceedings of the 7th international conference on Algorithms for Sensor Systems, Wireless Ad Hoc Networks and Autonomous Mobile Entities, ALGOSENSORS'11, pages 188{201, Berlin, Heidelberg, 2012. Springer-Verlag. [7] R.-E. Fan, K.-W. Chang, C.-J. Hsieh, X.-R. Wang, and C.-J. Lin. Liblinear: A library for large linear classi cation. J. Mach. Learn. Res., 9:1871{1874, June 2008. [8] R. F. Freitas and W. W. Wilcke. Storage-class memory: The next storage system technology. IBM Journal of Research and Development, 52(4.5):439 {447, july 2008. [9] D. Im, J. Lee, S. Cho, H. An, D. Kim, I. Kim, H. Park, D. Ahn, H. Horii, S. Park, U.-I. Chung, and J. Moon. A uni ed 7.5nm dash-type con ned cell for high performance pram device. In Electron Devices Meeting, 2008. IEDM 2008. IEEE International, pages 1 {4, dec. 2008. [10] M. Joshi, W. Zhang, and T. Li. Mercury: A fast and energy-e cient multi- level cell based phase change memory system. In High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, pages 345 {356, feb. 2011. [11] I. Kim, S. Cho, D. Im, E. Cho, D. Kim, G. Oh, D. Ahn, S. Park, S. Nam, J. Moon, and C. Chung. High performance pram cell scalable to sub-20nm technology with below 4f2 cell size, extendable to dram applications. In VLSI Technology (VLSIT), 2010 Symposium on, pages 203 {204, june 2010. [12] H. Kopetz and J. Reisinger. The non-blocking write protocol nbw: A solution to a real-time synchronization problem. In Real-Time Systems Symposium, 1993., Proceedings., pages 131 {137, dec 1993. [13] H. Li, Y. Xiong, and J. Ma. Overtmpfs: A virtual memory le system based on tmpfs. In Computer Science and Network Technology (ICCSNT), 2011 In- ternational Conference on, volume 4, pages 2712 {2715, dec. 2011. [14] N. Lu, I.-S. Choi, S.-H. Ko, and S.-D. Kim. An e ective hierarchical pram-slc- mlc hybrid solid state disk. In Proceedings of the 2012 IEEE/ACIS 11th In- ternational Conference on Computer and Information Science, ICIS '12, pages 113{118, Washington, DC, USA, 2012. IEEE Computer Society. [15] A. Patel, F. Afram, S. Chen, and K. Ghose. Marss: A full system simulator for multicore x86 cpus. In Design Automation Conference (DAC), 2011 48th ACM/EDAC/IEEE, pages 1050 {1055, june 2011. [16] R. Schaller. Technological innovation in the semiconductor industry: A case study of the international technology roadmap for semiconductors (itrs). In Management of Engineering and Technology, 2001. PICMET '01. Portland In- ternational Conference on, volume 1, page 195 vol.1, 2001. [17] D.-S. Suh, K. Kim, J.-S. Noh, W.-C. Shin, Y.-S. Kang, C. Kim, Y. Khang, and L. Yoo. Critical quenching speed determining phase of ge2sb2te5 in phase{ change memory. In Electron Devices Meeting, 2006. IEDM '06. International, pages 1 {4, dec. 2006. [18] J. Wang, X. Dong, G. Sun, D. Niu, and Y. Xie. Energy-e cient multi-level cell phase-change memory system with data encoding. In Computer Design (ICCD), 2011 IEEE 29th International Conference on, pages 175 {182, oct. 2011. [19] X. Wu and A. L. N. Reddy. Scmfs: a le system for storage class memory. In Proceedings of 2011 International Conference for High Performance Comput- ing, Networking, Storage and Analysis, SC '11, pages 39:1{39:11, New York, NY, USA, 2011. ACM. [20] W. Xu, J. Liu, and T. Zhang. Data manipulation techniques to reduce phase change memory write energy. In Proceedings of the 14th ACM/IEEE inter- national symposium on Low power electronics and design, ISLPED '09, pages 237{242, New York, NY, USA, 2009. ACM. [21] P. Zeitzo . Circuit, mosfet, and front end process integration trends and chal- lenges for the 180 nm and below technology generations: an international tech- nology roadmap for semiconductors perspective. In Solid-State and Integrated- Circuit Technology, 2001. Proceedings. 6th International Conference on, vol- ume 1, pages 23 {28 vol.1, 2001. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63955 | - |
dc.description.abstract | 現今的系統大多用動態主記憶體(DRAM)當作硬碟(Disk)的一個緩衝(Buffer)用的快取(Cache),這種做法是將資料與檔案暫時的存在主記憶體(Main memory)中,由於隨著技術與製程的進步,動態主記憶體與硬碟的之間的效能有著明顯的差距,已經形成一個鴻溝,而存取效能較慢的硬碟更常常成為提升整體系統的效能的一個瓶頸,因此,如何有效的減少兩種裝置之間的效能差距成了一個很重要的議題。
近年來相變化主記憶體(Phase Change Memory)成了一個熱門的研究對象,由其它的特性被認為可以有效的減少動態主記憶體與硬碟之間的鴻溝問題,本篇論文利用的相變化主記憶體的特性提供了一種計算機結構(architecture)的方式:熔合架構,藉由熔合架構,程式可以直接的存取相變化的資料而不必經過文件系統(File system)來處理,因此可以有效的提升系統效能。 | zh_TW |
dc.description.abstract | Computer systems use DRAM as a bu er cache for disk to temporarily load le's
data into main memory. But since the two devices have di erent access latency, the performance gap and the slower device will become a bottleneck that slows down the system's performance so that reduce the performance gap is a very important issue. In recent research, phase change memory (PRAM) is been believed that it will reduce the distinctions between memory and storage. In this work, we provide an architecture approach Fusion based on PRAM's features, by allowing programs to directly access les on PRAM with load store instructions and bypass le systems to get impressive performance improvement. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:24:17Z (GMT). No. of bitstreams: 1 ntu-101-R99922080-1.pdf: 1339632 bytes, checksum: 3c2ba576f670891a15652f4ba33a8c87 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | Contents
Abstract i 1 Introduction 1 2 Background and Related Works 3 2.1 PRAM background knowledge . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Related work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Fusion Architecture 12 3.1 Design principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.1 Fusion overview . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1.2 fusion architecture layout . . . . . . . . . . . . . . . . . . . . 14 3.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.1 Tmpfs on PRAM . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2.2 System call fmap . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.2.3 Workload modication . . . . . . . . . . . . . . . . . . . . . . 19 3.3 Workload modify guide line . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Summarize . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4 Evaluation 25 4.1 Experimental environment . . . . . . . . . . . . . . . . . . . . . . . . 4.1.1 environmental setup . . . . . . . . . . . . . . . . . . . . . . . 25 4.1.2 simulation tools . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 Evaluation methodology . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.3 Real workloads experiment result performance analyze . . . . . . . . 29 5 Conclusion 32 Bibliography 33 | |
dc.language.iso | en | |
dc.title | 熔合架構:相變化記憶體運用之主記憶體階層設計 | zh_TW |
dc.title | Fusion Architecture: A New Memory Hierarchy Design Using
Phase Change Memory | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 徐慰中(Wei-Chung Hsu),蘇雅韻(Ya-Yunn Su),王成淵 | |
dc.subject.keyword | 相變化主記憶體,動態主記憶體,快取,緩衝區,硬碟,計算機架構,文件系統, | zh_TW |
dc.subject.keyword | Phase Change Memory,DRAM,cache,buffer,disk,architecture,file system, | en |
dc.relation.page | 35 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-16 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊工程學研究所 | zh_TW |
顯示於系所單位: | 資訊工程學系 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-101-1.pdf 目前未授權公開取用 | 1.31 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。