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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 呂良鴻(Liang-Hung Lu) | |
| dc.contributor.author | Wei-Hsiu Hung | en |
| dc.contributor.author | 洪偉修 | zh_TW |
| dc.date.accessioned | 2021-06-16T17:21:13Z | - |
| dc.date.available | 2017-07-01 | |
| dc.date.copyright | 2012-08-20 | |
| dc.date.issued | 2012 | |
| dc.date.submitted | 2012-08-16 | |
| dc.identifier.citation | [1] M. I. Skolnik, Introduction to Radar Systems, 3rd edition. New York, NY: McGraw-Hill, 2001
[2] T. O. Jones, D. M. Grimes, and R. A. Dork, “A critical review of radar as a predictive crash sensor,” SAE Paper 720424, presentation given at 2nd Int. Conf. of Passive Restraints, Detroit, Mich., May 22-25, 1972 [3] Y. Kawano, A. Mineyama, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, “A Fully-Integrated K-band CMOS Power Amplifier with Psat of 23.8 dBm and PAE of 25.1 %,” in IEEE MTT-S Radio-Frequency Integrated Circuit (RFIC) Symp. Dig., Jun. 2011, pp.1-4 [4] P.-C. Huang, J.-L. Kuo, Z.-M. Tsai, K.-Y. Lin, and H. Wang, “A 22-dBm 24-GHz power amplifier using 0.18-μm CMOS technology,” in IEEE MTT-S Int. Microwave Symp. (IMS) Dig., Jun. 2010, pp. 248-251 [5] A. Afsahi, A. Behzad, and L. E. Larson, “A 65nm CMOS 2.4GHz 31.5dBm Power Amplifier with a Distributed LC Power-Combining Network and Improved Linearization for WLAN Applications,” in IEEE Intl. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, Feb. 2010, pp. 452-454 [6] P. Reynaert and A. M. Niknejad, “Power combining techniques for RF and mm-wave CMOS power amplifiers,” in Proc. European Solid-State Circuits Conf. (ESSCIRC), Sep. 2007, pp. 272–275 [7] T. Mitomo, N. Ono, H. Hoshino, Y. Yoshihara, O. Watanabe, and I. Seto, 'A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications,' IEEE J. Solid-State Circuits, vol.45, no.4, pp.928-937, April 2010 [8] W. Rhee, B.-S. Song, and A. Ali, 'A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator,' IEEE J. Solid-State Circuits, vol.35, no.10, pp.1453-1460, Oct 2000 [9] B. Miller and R.J. Conley, 'A multiple modulator fractional divider,' IEEE Transactions on Instrumentation and Measurement, vol.40, no.3, pp.578-583, Jun 1991 [10] R. Gu and S. Ramaswamy, 'Fractional-N phase locked loop design and applications,' in Proc. 7th International Conference on ASIC (ASICON), Oct. 2007, pp.327-332 [11] M. Kozak and I. Kale, 'Rigorous analysis of delta-sigma modulators for fractional-N PLL frequency synthesis,' IEEE Transactions on Circuits and Systems I: Regular Papers, vol.51, no.6, pp. 1148- 1162, June 2004 [12] C.-Y.Yang, G.-K. Dehng, J.-M. Hsu, and S.-I. Liu, 'New dynamic flip-flops for high-speed dual-modulus prescaler,' IEEE J. Solid-State Circuits, vol.33, no.10, pp.1568-1571, Oct 1998 [13] C. Vaucher and D. Kasperkovitz, 'A wide-band tuning system for fully integrated satellite receivers ,' IEEE J. Solid-State Circuits, vol.33, no.7, pp.987-997, Jul 1998 [14] W. Rhee, 'Design of high-performance CMOS charge pumps in phase-locked loops ,' in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), vol.2, Jul 1999, pp.545-548 [15] A. Djemouai, M. A. Sawan, and M. Slamani, “New frequency-locked loop based on CMOS frequency-to-voltage converter: Design and implementation,” IEEE Trans. Circuits and System II, Analog Digital Signal Process., vol. 48, no. 5, pp. 441–449, May 2001 [16] J. A. Michaelsen and D. T. Wisland, “Digital PVT calibration of a Frequency-to-Voltage Converter,” in Proc. NORCHIP Conference 2010, Nov. 2010 [17] C.-F. Liang, S.-H. Chen, S.-I. Liu , 'A Digital Calibration Technique for Charge Pumps in Phase-Locked Systems,' IEEE J. Solid-State Circuits, vol.43, no.2, pp.390-398, Feb. 2008 [18] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th edition. New York, NY: Oxford University Press, Inc. 2004 [19] L. H. Eriksson, “A Radar Sensor For Automatic AICC,” in Proc. IEEE 44th Veh. Tech. Conf., vol.1, Jun. 1994, pp. 434-437 [20] M. Ferndahl, T. Johansson, and H. Zirath, “20 GHz power amplifier design in 130 nm CMOS,” in Proc. of IEEE Euro. Microwave Integrated Cir. Conf. (EuMIC), Oct. 2008, pp. 254-257 [21] H.-T. Wu, R. Han, W. Lerdsitsomboon, C. Cao, and Kenneth K. O, “Multi-level amplitude modulation of a 16.8-GHz class-E power amplifier with negative resistance enhanced power gain for 400-Mbps data transmission,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp.1072-1079, May 2010 [22] Y.-C. Hsu, Y.-S. Chen, T.-C. Tsai, and K.-Y. Lin, “A K-band CMOS Cascode Power Amplifier Using Optimal Bias Selection Methodology,” in Proc. of Asia-Pacific Microwave Conf. (APMC), Dec. 2011, pp. 793-796 [23] J. Yang, G. Pyo, C.-Y. Kim, and S. Hong, “A 24-GHz CMOS UWB Radar Transmitter With Compressed Pulses,” IEEE Trans. on Microwave Theory and Techniques, vol. 60, No.4, pp. 1117-1125, Apr. 2012 [24] A. Scuderi, E. Ragonese, and G. Palmisano, “24-GHz ultra-wideband transmitter for vehicular short-range radar applications,” IET Circuits, Devices & Systems, vol. 3, issue 6, pp. 313-321, 2009 [25] H. Krishnaswamy and H. Hashemi, “A 4-Channel 24-27 GHz UWB Phased Array Transmitter in 0.13μm CMOS for Vehicular Radar,” in IEEE Custom Integrated Circuits Conference (CICC), Sep. 2007, pp. 753-756 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63863 | - |
| dc.description.abstract | 隨著車載安全設備日漸受到重視，24 GHz 防撞雷達有機會成為各式車輛的標準配備。目前，由於輸出功率與可靠度考量，該種雷達的發射機前端電路大多以三-五族製程實現。然而，該製程過高的成本讓防撞雷達無法普及，也使得低價的版本成為值得發展的目標。
在本篇論文中提出了以互補式金氧半導體製程達成系統整合的方法，以減低總製造成本。互補式金氧半導體製程已被用在多樣化的電路中，但隨著製程世代演進，其崩潰電壓也逐步下降，致使電晶體的輸出功率不足。在本次的前端電路設計中採用了功率結合的技巧，以得到較大的總輸出功率與足夠的雷達偵測距離。實作的前端電路可在K band提供17 dBm以上的輸出功率與最大29%的功率增加效率。 將此前端電路與一除小數的頻率合成器結合後，便可得到一個高整合度的雷達發射機。該頻率合成器可以合成出防撞雷達常用的頻率調變連續波波形，而多級雜訊整型的技巧則用來抑制以簡單累加器達成除小數功能時，在輸出頻譜上會出現的混附訊號。雷達系統的處理器可經由頻率合成器提供的數位控制介面控制連續波的調變速率與頻率範圍。 在前述發射機中，石英振盪器是唯一的非整合元件。若將其省去，則可造出更低成本的雷達發射機。在新的電路架構中，發射的連續波由一三角波產生器直接控制線性壓控震盪器產生。石英振盪器所提供的精準頻率由一校正迴圈取代，而此校正迴圈具有溫度變異不敏感的特性。此迴圈監視發射機的輸出頻率，並由壓控振盪器的調頻帶接腳進行回授控制。以此方法製造的發射機，其輸出訊號頻率將能落在所指定的頻率範圍中。 | zh_TW |
| dc.description.abstract | With the increasing emphasis on automobile safety, the 24-GHz collision avoidance radar emerges as a product that is likely to enjoy commercial success. Presently, due to output power and reliability requirements, the transmitter front-end of the radar is mainly fabricated with III-V process. However, the resulting high implementation cost impedes mass deployment. Therefore, a low-cost solution is desired to make the radar affordable.
In this thesis, the cost reduction is achieved through system integration, and CMOS technology is chosen to carry out the challenge. The CMOS process is known for its unparalleled versatility, but its break-down voltage decreases with the shrinking of the feature size, leading to insufficient output power from a single device. Therefore, the power-combining techniques are introduced in the implementation of the CMOS front-end circuit to join the output power from several devices, which guarantees the detection range of the radar. The fabricated front-end circuit provides above-17-dBm output power in the allocated K band and reaches a maximum power-added efficiency (PAE) of 29%. Based on the front-end circuit, a highly-integrated transmitter is realized with the addition of a fractional-N frequency synthesizer. The synthesizer is capable of producing the frequency-modulated continuous wave (FMCW) signal that is commonly employed in the collision avoidance radar application. The spurious tones that would present in a simple accumulator-based fractional-N function realization are suppressed by the incorporation of multi-stage noise shaping (MASH) technique. The synthesizer provides a digital control interface, and the system processor is allowed to change the sweep range and sweep time of the FMCW signal through this interface. In order to further reduce the cost of the transmitter, the bulky and out-of-chip crystal oscillator (XO) that is essential in the realization of frequency synthesizer is proposed to be removed. The FMCW signal is generated by a triangular waveform generator directly modulating a linear-tuning voltage-controlled oscillator (VCO). The precise frequency definition provided by the XO is replaced by a temperature-variation- insensitive calibration loop, which monitors the output signal frequency and provides feedback through the band-switching function of the VCO. Thus, the output signal of the crystal-less transmitter will remain within the allocated frequency band. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T17:21:13Z (GMT). No. of bitstreams: 1 ntu-101-R99943002-1.pdf: 31061114 bytes, checksum: d46c912afcd2ac77b97650a71ecd6942 (MD5) Previous issue date: 2012 | en |
| dc.description.tableofcontents | 口試委員會審定書 ...........................................i
致謝 ...................................................iii 摘要 .....................................................v Abstract ..............................................vii List of Figures.........................................xi List of Tables..........................................xv Chapter I. Introduction .................................1 1.1 Motivation.........................................1 1.2 Thesis Organization................................2 Chapter II. CMOS FMCW Radar Fundamentals.................3 2.1 FMCW Principles....................................3 2.2 The Radar Equation.................................5 2.3 Design Challenges..................................7 2.4 CMOS Power Amplifier...............................7 2.5 Fractional-N Frequency Synthesizer................10 2.6 Alternative Transmitter Architecture..............12 Chapter III. A 24-GHz FMCW Radar Transmitter Front-end 15 3.1 System Architecture ............................. 15 3.2 Circuit Implementation ...........................15 3.2.1 Class-AB power amplifier .....................15 3.2.2 Power-combining techniques....................18 3.2.3 Driving amplifiers ...........................21 3.2.4 Voltage-controlled oscillator ................22 3.3 Experimental Results .............................23 Chapter IV. A 24-GHz FMCW Radar Transmitter using Fractional-N Frequency Synthesizer ........ 27 4.1 System Architecture ..............................27 4.2 Circuit Implementation ...........................27 4.2.1 The delta-sigma modulator ....................27 4.2.2 Frequency synthesizer system parameters ......31 4.2.3 Frequency synthesizer components .............32 4.3 Experimental Results .............................38 Chapter V. A Crystal-less 24-GHz FMCW Radar Transmitter 43 5.1 System Architecture ..............................43 5.2 System Operation .................................43 5.3 Circuit Implementation ...........................45 5.3.1 Frequency detector ...........................45 5.3.2 Comparator ...................................51 5.3.3 Successive-approximation logic block .........51 5.3.4 Triangular voltage waveform generator ........52 5.3.5 Timing control ...............................53 5.4 Experimental Results .............................54 Chapter VI. Conclusion .................................59 6.1 Future Work ......................................59 | |
| dc.language.iso | en | |
| dc.title | 24-GHz 互補式金氧半導體連續波雷達發射機設計與實作 | zh_TW |
| dc.title | Design and Implementation of 24-GHz CMOS FMCW Radar Transmitter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 100-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 林宗賢(Tsung-Hsien Lin),黃俊郎(Jiun-Lang Huang) | |
| dc.subject.keyword | 頻率調變連續波雷達,功率放大器,功率結合,除小數頻率合成器,無石英震盪器發射機, | zh_TW |
| dc.subject.keyword | FMCW radar,power amplifier,power combination,fractional-N frequency synthesizer,crystal-less transmitter, | en |
| dc.relation.page | 64 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2012-08-17 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
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| File | Size | Format | |
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| ntu-101-1.pdf Restricted Access | 30.33 MB | Adobe PDF |
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