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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李坤彥 | |
dc.contributor.author | Cheng-Yueh Chung | en |
dc.contributor.author | 鍾呈岳 | zh_TW |
dc.date.accessioned | 2021-06-16T17:13:40Z | - |
dc.date.available | 2012-08-21 | |
dc.date.copyright | 2012-08-21 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-20 | |
dc.identifier.citation | [1]鄭晃忠, 劉傳璽主編, ”新世代積體電路製程技術” , p.176, 2011.
[2]J. Robertson, “electronic structure and band offsets of high-dielectric-constant gate oxides”, mater. Research Soc, vol.27, pp.217-221, 2002. [3]J. Robertson, ”band offset of wide-band-gap oxides and implications for future electronic devices”, 'J.vac.sci.technol.B, vol.18, pp.1785-1791, 2000. [4]G. D. Wilk, RM. Wallace, and J. M. Athony, 'high-k gate dielectrics current status and Materials properties concsiderations', J. appl. phys., vol.89, pp.5243-5275, 2001. [5]Microelectronics, Serbia and Montenegro, vol.1, NIS, pp.16-19, 2004. [6]G. R. Fisher and P. Barnes, Phil. Mag, B 61, 217 1990. [7]H. S. Lee, 'High power bipolar Junction Transistor in Silicon Carbide,' ISRN KTH/EKT/FR-2005/6-SE. [8]J. McPherson, J. Kim Ashware, H. Mogul, and J. Rodriguez, 'proposed Universal relation between dielectric breakdown and dielectric constant' , in IEEE IEDM Tech.Dig., pp.633-636, 2002. [9]S. M. Sze, “Physics of Semiconductor Devices”, Wiley &Sons Inc., New Caledonia, pp.197-200, 2007. [10]S. M. Sze, “Physics of Semiconductor Devices”, Wiley &Sons Inc., New Caledonia, pp.170-174, 2001. [11]S. M. Sze, ”Physics of Semiconductor Devices”, Wiley &Sons Inc., New Caledonia, pp.181-182, 2001. [12]M. T. Bohr et al., “the high-k solution”, IEEE spectrum, vol.44, pp.29-35, 2007. [13]T. Hori, “Gate Dielectrics and MOS ULSIs Springer-Verlag”, New york, pp.44-46, 1977. [14]C. Durand, C. Valle’ e, V. Loup, and O. Salicio, “Metal–insulator–metal capacitors using Y2O3 dielectric grown by pulsed-injection plasma enhanced metal organic chemical vapor deposition”, Journal of Vacuum Science Technology, vol.22, Issue 3, pp.655-660, 2004. [15]L. Manchanda, M. Gurvitch, IEEE Electron Device Lett.9, 180, 1988. [16]S. Guha, E. Cartier, M. A. Gribelyuk, N. A. Borjarczuk, and M. A. Copel, Appl. Phys.Lett.77, 2710, 2000. [17]G. D. Wilk, R. M. Wallace, J.M. Athony, ”high-k gate dielectrics Current status and Materials Properties Considerations”, J. Appl. phys. vol.89, pp.5243-5275, 2001. [18]W. J. Qi, et al., ”MOSCAP and MOSFET Characteristics Using ZrO2 Gate Dielectric Deposited Directly on Si”, in IEDM Tech. Dig, pp.145-148, 1999. [19]C. H. Liu and P. C. Juan, Y. H. Chou, and J. Y. Lin, ”The effect of lanthanum(La) incorporation in Ultra-Thin ZrO2 High-k Gate dielectrics”, in International Conference on Electronic Materials, PI-315, 2010. [20]Data sheet of SPR-220 Series Photoresist, p2. [21]S. Dhar, L. C. Feldman, S. Wang, T. Isaacs-Smith, and J. R. Williams, “Interface trap passivation for SiO2/(000) C-terminated 4H-SiC”, J.Appl.Phys.98,014902, 2005. [22]S. M. Sze, Physics of Semiconductor Devices. Wiley &Sons Inc., New Caledonia. pp.235, 2001. [23]M.-H. Cho, D.-H. Ko, K. Jeong, I. W. Lyo, S. W. Whangbo et al., ” Temperature dependence of the properties of heteroepitaxial Y2O3 films grown on Si by ion assisted evaporation”, J. Appl. Phys. 86, 198, 1999. [24]A. Dimoulas, G. Vellianitis, A. Travlos, V. Ioannou-Sougleridis, and A. G. Nassiopoulou, ”Structural and electrical quality of the high-k dielectric Y2O3 on Si (001):Dependence on growth parameters”, J. Appl. Phys. 92, 426, 2002. [25]A. Tesfaye, “SiC Semiconductor Devices Technology, Modeling, and Simulation”, Dissertation, Universitat Wien Fakultat fur Elektrotechnik and Informationstechnik, 2004. [26]W. A. Hill and C. C. Coleman, “A single-frequency approximation for interface state density determination”, Solid-State Electronics, vol.23, pp.987-993, 1980. [27]E. Miranda, E. O’Connor, K. Cherkaoui, S. Monaghan, R. Long, D. O’Connell, P. K. Hurley, G. Hughes, and P. Casey,” Electrical characterization of the soft breakdown failure mode in MgO layers”, Appl. Phys. Letts., 95, 2009.[28]M.K. Radhakrishnan, K.L. Pey, C.H. Tung c, W.H. Lin,” Physical analysis of hard and soft breakdown failures in ultrathin gate oxides”, Microelectronics Reliability, 42,pp.565–571, 2002. [29]J. Robertsona,” High dielectric constant oxides”, Eur. Phys. J. Appl. Phys.,28,pp.265–291, 2004. [30]Jae Hwan Ko, Soo Ho Kim, Seung Hyun Jee and Young Soo Yoon, ” Characteristics of ZrO2 Thin Films Deposited by Reactive Magnetron Sputtering” , Journal of the Korean Physical Society, vol.50, No.6, pp.1843-1847, 2007. [31]Keunbin Yim, Yeonkyu Park, Anna Park, Namhee Cho and Chongmu Lee,” Electrical Properties of Sputter-deposited ZrO2-based Pt/ZrO2/Si Capacitors”, J. Mater. Sci. Technol., vol.22, 2006. [32]Kenichi Onisawa, Moriaki Fuyama, Katsumi Tamura, Kazuo Taguchi, Takahiro Nakayama et al, ” Dielectric properties of rfsputtered Y2O3 thin films”, J. Appl. Phys. 68, 719, 1990. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63533 | - |
dc.description.abstract | 本論文製作兩種金氧半電容元件,基板使用4H-SiC,氧化層使用ZrO2和Y2O3為閘極氧化層,等效於SiO2厚度為10nm,閘極使用鋁閘極,我們使用四種不同的溫度條件,基板在常溫下和基板加熱200℃及沒有退火和快速熱退火溫度500℃的組合。可以得到四種溫度環境。基板室溫加不退火;基板不加熱加退火溫度500℃;基板加熱200℃加不退火,基板加熱200℃加退火溫度500℃。
可以得到漏電流關係在Y2O3基板不加熱、不退火,電場強度為1MV/cm是10-1A/cm2,在基板加熱200℃、不退火,電場強度為1MV/cm時,漏電流為10-3A/cm2,基板不加熱、快速熱退火溫度500℃或加熱基板200℃、快速熱退火溫度500℃,電場強度為1MV/cm時,漏電流密度都是10-6A/cm2。ZrO2基板不加熱、沒有退火,電場強度為1MV/cm時,漏電流密度是10-1A/cm2,在基板加熱200℃、不退火,電場強度為1MV/cm時,漏電流密度為10-3A/cm2,基板不加熱或基板加熱200℃、快速熱退火溫度皆為500℃,電場強度為1MV/cm時,漏電流密度都是10-7A/cm2,至於C-V量測方面,在兩種薄膜的電容情況,平帶電壓有的偏移現象,可能是濺鍍造成過多的氧化層電荷在氧化層中堆積,形成偏移,但經由快速熱退火製程有達到減少氧化層電荷的作用。 | zh_TW |
dc.description.abstract | In this research, we design two kinds of MOS-Capacitors with ZrO2 and Y2O3 as the insulators. (Equivalent Oxide Thickness, EOT) EOT is 10nm.Therefore, ZrO2 and Y2O3 were deposited on substrates at different substrate temperature (room temperature and 200℃) and then (Rapid Thermal annealing, RTA) at 500℃.We can get four kinds of temperature conditions. Condition1:Tsubtrate is room temperature, and Tannealing is room temperature. Condition2:Tsubtrate is room temperature, and Tannealing is 500℃.Condition3:Tsubtrate is 200℃. and Tannealing is room temperature.Condition4:Tsubtrate is 200℃,and Tannealing is 500℃.
We report the C-V, I-V electrical measurement results of MOS capacitors using Y2O3 thin film deposited by RF sputtering. The leakage current density is about 10-3A/cm2 at 0.5MV/cm in condition 1.The leakage current density is about 10-3A/cm2 at 1MV/cm in condition 2.The leakage current density is about 10-3A/cm2 at 1.5MV/cm in condition 3.The leakage current density is about 10-3A/cm2 at 1.6MV/cm in condition 4.ZrO2 thin film deposited by RF sputtering. The leakage current density is about 10-3A/cm2 at 0.5MV/cm in condition 1. The leakage current density is about 10-3A/cm2 at 1MV/cm in condition 2. The leakage current density is about 10-3A/cm2 at 0.8MV/cm in condition 3. The leakage current density at 1MV/cm is about 10-3A/cm2 at 2.7MV/cm in condition 3, and condition 4. According to the results, the ZrO2 thin film is better than Y2O3 for the leakage current. the C-V measurement result of MOS capacitors using Y2O3 and MOS capacitors using ZrO2,the flat band voltage is shift. The possible reason is more fixed oxide charge and mobile ion charge in oxide layer. We have reduced charge in oxide layer by RTA process. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T17:13:40Z (GMT). No. of bitstreams: 1 ntu-101-R99525026-1.pdf: 3040820 bytes, checksum: 0321df9850586238e5ccc36d8202c50a (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 中文摘要 ii ABSTRACT iii 論文大綱 iv 圖目錄 vii 表目錄 xi Chapter 1 緒論 1 1.1 前言 1 1.2 碳化矽材料及特性介紹 2 1.3 高介電係數介電層 4 1.4 論文大鋼 6 Chapter 2 理論背景 7 2.1 金氧半電容 7 2.1.1 金氧半電容 (MOS- capacitor) 簡介 7 2.1.2 金氧半電容操作原理 8 2.1.3 氧化層缺陷 12 2.1.4 電性量測 14 2.2 高介電係數材料 16 2.2.1 高介電係數材料的應用 18 2.2.2 閘極氧化層的選擇 18 2.2.3 氧化釔材料 19 2.2.4 二氧化鋯材料 20 2.3 薄膜沉積 20 2.3.1 薄膜沉積簡介 20 2.3.2 濺鍍 (sputtering) 21 2.3.3 直流濺鍍(DC sputtering) 21 2.3.4 射頻濺鍍(RF sputtering) 21 2.4 量測機台簡介 22 2.4.1 X光繞射儀量測 (XRD) 22 2.4.2 探針式表面分析儀量測 (Probe-type surface analyzer) 23 Chapter 3 MOS-C元件製作 25 3.1 光罩設計 26 3.2 晶片清洗 27 3.3 氧化層薄膜成長 29 3.3.1 濺鍍機特性 29 3.3.2 Y2O3薄膜成長時間 29 3.3.3 ZrO2薄膜成長時間 30 3.3.4 濺鍍程序 30 3.4 晶片快速熱退火(RTA) 30 3.5 閘極金屬電極製作使用lift off法 32 Chapter 4 量測與結果討論 38 4.1 霍爾量測分析 38 4.1.1 量測晶片濃度 38 4.2 XRD分析 43 4.3 電容-電壓分析 46 4.3.1 電容-電壓(C-V)電性分析 46 4.3.2 不同溫度環境下電壓-電容關係 51 4.3.3 再次熱處理後電容電壓曲線 55 4.4 電流-電壓(I-V)特性量測 58 4.4.1 Y2O3電流-電壓特性 58 4.4.2 ZrO2電流-電壓特性 63 Chapter 5 結論與未來展望 68 REFERENCE 69 | |
dc.language.iso | zh-TW | |
dc.title | 二氧化鋯、氧化釔4H碳化矽金氧半電容製作及分析 | zh_TW |
dc.title | Fabrication and analysis of 4H-SiC MOS Capacitor with High-k Gate Dielectrics:ZrO2,Y2O3 | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃智方,李佳翰 | |
dc.subject.keyword | 金氧半電容,碳化矽,射頻濺鍍,閘極氧化層,快速熱退火,氧化釔,二氧化鋯, | zh_TW |
dc.subject.keyword | MOS-capacitor,SiC,RF sputter,Gate insulators,RTA,Y2O3,ZrO2, | en |
dc.relation.page | 71 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-20 | |
dc.contributor.author-college | 工學院 | zh_TW |
dc.contributor.author-dept | 工程科學及海洋工程學研究所 | zh_TW |
顯示於系所單位: | 工程科學及海洋工程學系 |
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