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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李德財(Der-Tsai Lee) | |
dc.contributor.author | I-Hua Lin | en |
dc.contributor.author | 林奕樺 | zh_TW |
dc.date.accessioned | 2021-06-16T16:44:54Z | - |
dc.date.available | 2017-08-27 | |
dc.date.copyright | 2012-08-27 | |
dc.date.issued | 2012 | |
dc.date.submitted | 2012-08-20 | |
dc.identifier.citation | [1] C. M. Fiduccia and R. M. Mattheyses, “A linear time heuristic for improving network partitions”, in Proc.ACM/IEEE Design Automation Conf,
[2] G.Karypis, R.Aggarwal, V.Kumar, and S.Shekhar “Multilevel Hypergraph Partitioning: Applications in VLSI Domain”, IEEE Trans. VLSI Syst. Vol.7, pp.69-79, 1999. [3] CAD Contest, Three-Dimensional Integrated Circuit Partitioning with Power Consideration, 2011. [4] Neil H. E. Weste and Kamran Eshraghian, Principles of CMOS VLSI Design, A Systems Perspective, second ed. Addison Wesley, 1993. [5] Charles J. Alpert and Andrew B. Kahng, Recent directions in netlist partitioning: a survey. INTEGRATION, the VLSI journal, 19:1–81, 1995. [6] Yuan Xie, Bryan Black and Kerry Bernstein, Design Space Exploration for 3D Architectures, 2006 [7] Andrew E. Caldwell, Andrew B. Kahng, and Igor L. Markov, Design and Implementation of the Fiduccia-Mattheyses Heuristic for VLSI Netlist Partitioning, 1999 [8] Sahar Idwan and Wael Etaiwi, “Computing Breadth First Search in Large Graph Using hMetis Partitioning”, European Journal of Scientific Research, 2009 [9] Charles J. Alpert, Jen-Hsin Huang, and Andrew B. Kahng, “Multilevel circuit partitioning”, IEEE ICCAD, 1998. [10] George Karypis and Vipin Kumar, “Multilevel k-way Partitioning Scheme for Irregular Graphs” J. Parallel Distrib. Comput. 48(1): 96-129, 1998 [11] Yole Development “3D TSV Interconnects Devices & Systems - 2008 Report”, www.yole.fr. [12] Beyne, E., “3D System Integration Technologies”, VLSI Technology, Systems, and Applications, 2006 International Symposium on. [13] JM Rabaey, AP Chandrakasan, and B Nikolic, “Digital integrated circuits” 1996 didattica.arces.unibo.it [14] M. Santarini, “Thermal integrity: A must for low-power IC digital design,” in Proc. EDN, Sep. 2005, pp. 37–42. [15] Xiangyu Dong, Yuan Xie, 'System-level Cost Analysis and Design Exploration for 3D ICs', Asia and South Pacific Design Automation Conference, 2009. pp 234-241. [16] Banqiu Wu, Ajay Kumar, and Sesh Ramaswami, “3D IC Stacking Technology”, July. 2011. [17] Lewis, D. L. and H. H. S. Lee, “A scanisland based design enabling prebond testability in die-stacked microprocessors.” Test Conference, 2007. ITC 2007. IEEE International. [18] Yuan Xie, Jason Cong, and Sachin Sapatnekar, 'Three Dimensional Integrated Circuit Design',2010, Springer. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63486 | - |
dc.description.abstract | 隨著科技的發展,晶片的電路設計漸趨複雜,而人們對於電子產品的需求依舊是小而精巧,因此,為了解決二維積體電路(2D IC)面積的問題,以及縮短線長與增加可靠性等,三維積體電路(3D IC)的堆疊架構因應而生,其中,以矽穿孔道(Through Silicon Via, TSV)為基礎的堆疊結構最受重視。然而,三維積體電路的中間層散熱是一個急欲解決的技術問題。
在晶片設計完成與驗證之後,實體設計的電路分割(Circuit Partitioning )是重要的第一步;好的電路分割將能有效的縮短線長、降低成本,而分層的電量限制則能避免晶片過熱而產生運作問題;分割電路後,分層過程中所產生的切點(Cut)將需要透過高成本的矽穿孔道(TSV)來實現,因此,最小化矽穿孔道(TSV)的數量是我們首要的達成目標;而三維積體電路需要以最大面積的該層電路做為切割晶粒大小的依據,因此,藉由均衡電路面積分配,以減少晶片體積來降低成本,也是我們所需改善的方向。 因此,在本文中,我們修改一個二路的分割演算法(2-way FM Partitioning Algorithm ),使其成為多層分割演算法 (Multilayer FM-like Partitioning Algorithm),藉此解決三維積體電路分割問題,並且提供一個新的電量切割模型(Power-Cut Model),以進行考量電量的分割步驟;在實驗結果當中,我們實作了兩種不同的選點策略,藉此比較考量電量切割模型(Power-Cut Model)對於不同的分割演算法所產生的影響,其中,改良自原始的FM分割演算法的選點策略,3D IC相較於2D IC額外產生面積在10%以內,整體分割品質受到電量的影響程度較低;另一個選點策略則較能快速的獲得結果,面積平均程度由初始設定的面積係數所決定,分割品質受到電量的影響程度較高;此外,由實驗可知,電路本身的電密度與分割過程中受到電量的影響程度成正比。 | zh_TW |
dc.description.abstract | As the design of electronic product becomes more and more complicated, the area expansion of two-dimensional integrated circuit (2D IC) occupies too much space. Therefore, 3D IC stacked structure, connected by through-silicon-via (TSV), is used to effectively reduce the chip area and wire length.
However, the thermal problem in 3D IC requires immediate solution. The interlayer produces the thermal problem because only the top and the bottom layer are connected with the sink directly. The thermal problem can be solved by the power density constraint in interlayer because the degree of power density is related in thermal generation. The necessary stage in standard circuit design is partition; thus the partition with power consideration in 3D IC is important. In 3D IC partitioning, there are two major objectives, including minimizing the chip area and the number of the TSVs to reduce the manufacture cost. In this thesis, we use a multilayer FM-like partitioning algorithm with power model to achieve our objectives. To predict the power influence early in vertex-move step of the IC partition, we formulate the power density constraint by proposing a new power-cut model. The experiment results were analyzed in terms of the influence of the power effect. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T16:44:54Z (GMT). No. of bitstreams: 1 ntu-101-R98943150-1.pdf: 1907052 bytes, checksum: 7d520e69b74fe75c3907ef32ad79f8a1 (MD5) Previous issue date: 2012 | en |
dc.description.tableofcontents | 誌謝 i
中文摘要 ii ABSTRACT iii CONTENT iv LIST OF FIGURES vi LIST OF TABLES viii Chapter 1 Introduction 1 Chapter 2 Preliminaries 6 2.1 Literature Review 6 2.1.1 Three-Dimensional Integrated Circuit Development 6 2.1.2 Power Average Model 9 2.2 Problem Formulation 14 Chapter 3 Three-Dimensional Integrated Circuit Partitioning with Power Cut Model 17 3.1 Multilayer FM-like Partitioning 18 3.1.1 Variables and Notation 18 3.1.2 Review of 2-way FM partitioning 19 3.1.3 Multilayer FM-like Partitioning 24 3.2 Power-Cut Model 34 3.2.1 Variables and Notation 34 3.2.2 Power-Cut Model Definition 35 3.2.3 Property of the Power-Cut Model 35 Chapter 4 Experiments 45 4.1 Experimental Design 45 4.2 Experimental Results 47 Chapter 5 Conclusion and Future Work 53 REFERENCES 54 | |
dc.language.iso | en | |
dc.title | 考量電量之三維積體電路分割演算法 | zh_TW |
dc.title | Three-Dimensional Integrated Circuit Partitioning with Power Consideration | en |
dc.type | Thesis | |
dc.date.schoolyear | 100-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 陳良基(Liang-Gee Chen),江介宏(Jie-Hong Jiang) | |
dc.subject.keyword | 三維積體電路(3D IC),穿矽孔道(TSV),電密度限制,散熱問題,FM分割演算法,超圖分割演算法,實體設計, | zh_TW |
dc.subject.keyword | Three-Dimensional Integrated Circuit (3D IC),Through Silicon Via (TSV),Power Density Constraint,Thermal Problem,FM Partitioning Algorithm,Hypergraph, | en |
dc.relation.page | 56 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2012-08-21 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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