請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63338完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 林宗賢(Tsung-Hsien Lin) | |
| dc.contributor.author | Yu-Ting Hung | en |
| dc.contributor.author | 洪宇廷 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:35:43Z | - |
| dc.date.available | 2020-06-09 | |
| dc.date.copyright | 2020-06-09 | |
| dc.date.issued | 2020 | |
| dc.date.submitted | 2020-04-28 | |
| dc.identifier.citation | [1] H. Lakdawala et al., “32nm x86 OS-compliant PC on-chip with dual-core Atom processor and RF WiFi transceiver,” in ISSCC Dig. Tech. Papers, Feb. 2012, pp. 62–64.
[2] J. Chien and L. Lu, “Ultra-Low-Voltage CMOS Static Frequency Divider,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2005, pp. 209–212. [3] P. Larsson and C. Svensson, “Impact of clock slope on true single phase clocked (TSPC) CMOS circuits,” IEEE J. Solid-State Circuits, vol. 29, no. 6, pp. 723–726, Jun. 1994. [4] O. Momeni, K. Sengupta, and H. Hashemi, “Regenerative Frequency Divider with Synchronous Fractional Outputs,” in Proc. IEEE Radio Freq. Integr. Circuits Symp., Jun. 2007, pp. 717–720. [5] M. Farazian, P. S. Gudem, and L. E. Larson, “Stability and Operation of Injection-Locked Regenerative Frequency Dividers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 2006–2019, Aug. 2010. [6] B. Razavi, “Heterodyne Phase Locking: A Technique for High-Frequency Division,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 428–429. [7] R. J. Betancourt-Zamora, S. Verma, and T.-H. Lee, “1-GHz and 2.8-GHz CMOS injection-locked ring oscillator prescalers,” in Symp. VLSI Circuits, Dig. Tech. Papers, Jun. 2001, pp. 47–50. [8] K. Yamamoto and M. Fujishima, “A 44-W 4.3-GHz injection-locked frequency divider with 2.3-GHz locking range,” IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. 671–677, Mar. 2005. [9] M. Tiebout, “A CMOS direct injection-locked oscillator topology as high-frequency low-power frequency divider,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1170–1174, Jul. 2004. [10] W. Chen and B. Jung, “High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 58, no.3, pp. 144–148, Mar. 2011. [11] A. Elkholy, S. Saxena, R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0–5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider,” IEEE J. Solid-State Circuits, vol. 51, no. 8, pp. 1771–1784, Aug. 2016. [12] Z. Gao, Y. Xu, P. Sun, E. Yao, and Y. Hu, “A programmable high-speed pulse swallow divide-by-N frequency divider for PLL frequency synthesizer,” in Proc. Int. Comput. Appl. Syst. Modeling Conf., Oct. 2010, vol. 6, pp. V6–315–V6–318. [13] C. Hsu, M. Z. Straayer, and M. H. Perrott, “A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 340–617. [14] D. Tasca, M. Zanuso, G. Marzin, S. Levantino, C. Samori, and A. L. Lacaita, “A 2.9–4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fsrms Integrated Jitter at 4.5-mW Power,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 2745–2758, Dec. 2011. [15] A. Elkholy, T. Anand, W. Choi, A. Elshazly, and P. K. Hanumolu, “A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC,” IEEE J. Solid-State Circuits, vol. 50, no. 4, pp. 867–881, Apr. 2015. [16] H. Mair and L. Xiu, “An architecture of high-performance frequency and phase synthesis,” IEEE J. Solid-State Circuits, vol. 35, no. 6, pp. 835–846, Jun. 2000. [17] Y.-H. Liu and T.-H. Lin, “An energy-efficient 1.5-Mbps wireless FSK transmitter with A Δ-modulated phase rotator,” in Proc. Eur. Solid-State Circuits Conf., Sep. 2007, pp. 488–491. [18] Y.-H. Liu and T.-H. Lin, “A Wideband PLL-Based G/FSK Transmitter in 0.18 μm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 9, pp. 2452–2462, Sep. 2000. [19] B. A. Floyd, “Sub-Integer Frequency Synthesis Using Phase-Rotating Frequency Dividers,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1823–1833, Aug. 2008. [20] S. Pellerano, P. Madoglio, and Y. Palaskas, “A 4.75-GHz Fractional Frequency Divider-by-1.25 With TDC-Based All-Digital Spur Calibration in 45-nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3422–3433, Dec. 2009. [21] J. Jin, X. Liu, T. Mo, and J. Zhou, “Quantization Noise Suppression in Fractional-N PLLs Utilizing Glitch-Free Phase Switching Multi-Modulus Frequency Divider,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 5, pp. 926–937, May 2012. [22] X. Liu, J. Jin, X. Li, and J. Zhou, “Glitch-free multi-modulus frequency divider for quantization noise suppression in fractional-N PLLs,” in Proc. Int. Symp. Circuits Syst., May 2011, pp. 478–481. [23] A. Elkholy, A. Elshazly, S. Saxena, G. Shu, and P. K. Hanumolu, “A 20-to-1000MHz ±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2014, pp. 272–273. [24] A. Elkholy, S. Saxena, G. Shu, A. Elshazly, and P. K. Hanumolu, “Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers,” IEEE J. Solid-State Circuits, vol. 53, no. 6, pp. 1806–1817, Jun. 2018. [25] S. Hung and S. Pamarti, “A 0.5-to-2.5GHz Multi-Output Fractional Frequency Synthesizer with 90fs Jitter and -106dBc Spurious Tones Based on Digital Spur Cancellation,” in ISSCC Dig. Tech. Papers, Feb. 2019, pp. 262–264. [26] M. Fonseca, E. Costa, S. Bambi, and J. Monteiro, “Design of a radix-2 hybrid array multiplier using carry save adder,” Symposium on Integrated Circuits and Systems Design, pp. 172-177, Sep. 2005. [27] C. Liu, S. Chang, G. Huang, and Y. Lin, “A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731–740, Apr. 2010. [28] H. Cho et al., “A 0.0047mm2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHz,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 154–155. [29] A. Li, Y. Chao, X. Chen, L. Wu, and H. C. Luong, “An inductor-less fractional-N injection-locked PLL with a spur-and-phase-noise filtering technique,” in Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2016, pp. 1–2. [30] L. Kong and B. Razavi, “A 2.4GHz RF fractional-N synthesizer with 0.25fREF BW,” in ISSCC Dig. Tech. Papers, Feb. 2017, pp. 330–331. [31] M. Lee et al., “A 0.3-to-1.2V frequency-scalable fractional-N ADPLL with a speculative dual-referenced interpolating TDC,” in ISSCC Dig. Tech. Papers, Feb. 2018, pp. 122–124. [32] H. Liu et al., “A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2019, pp. 256–258. [33] H. Liu et al., “A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of −246dB for IoT applications in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2018, pp. 246–248. [34] X. Gao et al., “A 2.7-to-4.3GHz, 0.16psrms-jitter, −246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2016, pp. 174–175. [35] T. Jang et al., “A 0.026mm2 5.3mW 32-to-2000MHz digital fractional-N phase locked-loop using a phase-interpolating phase-to-digital converter,” in ISSCC Dig. Tech. Papers, Feb. 2013, pp. 254–255. [36] Si5335B datasheet, Silicon Labs. [37] 5P49V5923 datasheet, Integrated Device Technology. [38] J. Z. Ru, C. Palattella, P. Geraedts, E. Klumperink, and B. Nauta, “A High-Linearity Digital-to-Time Converter Technique: Constant-Slope Charging,” IEEE J. Solid-State Circuits, vol. 50, no. 6, pp. 1412–1423, Jun. 2015. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63338 | - |
| dc.description.abstract | 近年來，由於積體電路的快速演進，在高科技電子產品當中常常會包含許多系統晶片。而一個系統晶片往往又由各種不同的子晶片或是記憶體所組成。這些子晶片以及記憶體通常需要各種不同頻率的輸入時脈。在傳統的系統晶片中，每一種不同的時脈都需要一個鎖相迴路配合以便提供穩定而且準確的頻率。然而，大量使用鎖相迴路於一個系統晶片中不但占據大量面積而且消耗巨大功率，如果能使用多個小數輸出除頻器搭配單一鎖相迴路即可解決以上所提到的問題。
本作品為一個以數位對時間轉換器為基底之開迴路小數除頻器，其輸出頻率範圍為0.625-200百萬赫茲。此作品的應用為提供時脈給單一系統晶片內，操作於不同頻率的子電路，以維持正常操作。以單一時脈產生器搭配數個本作品之除頻器，可以節省多個不同頻率時脈產生器的面積以及功率消耗。本作品以台積電 90奈米製程實現。量測結果顯示在不同的除數下，本作品能正確地操作。輸出訊號量測得到之均方根時基誤差(RMS Jitter)在校正電路完成校正之後約為120飛秒，而此作品在1伏特的操作電壓下，最大功率消耗為1.45毫瓦。除此之外，此作品還可以同時支援展頻的功能。 | zh_TW |
| dc.description.abstract | A system-on-chip (SoC) usually consists of multiple subsystems. These subsystems operate at different clock frequencies. In conventional solution, each subsystem needs a phase-locked loop (PLL) for generating stable and accurate frequency. However, using multiple PLLs in a system consume large chip area and high power consumption. An alternative method which uses only one PLL and several fractional output dividers can solve the problem mentioned above.
This thesis presents “a 0.625~200 MHz DTC-based open loop fractional output divider”. This work supports wide output frequency range. This chip is fabricated in TSMC 90-nm CMOS technology. The measurement results show that the proposed fractional output divider operates properly both in the integer mode and fractional mode. The measured RMS Jitter is 120 fs when the calibration circuit is finished. The overall power consumption of this work is 1.45 mW under 1-V supply voltage. Furthermore, this work can support the required clocking function for spread spectrum. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:35:43Z (GMT). No. of bitstreams: 1 ntu-109-R05943177-1.pdf: 5179770 bytes, checksum: 7e424740d259c2b390a359ed61c328fa (MD5) Previous issue date: 2020 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii Table of Contents iii List of Figures v List of Tables x Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Overview 1 Chapter 2 Architectures of Frequency Division 2 2.1 Frequency Division 2 2.1.1 Static Frequency Divider 2 2.1.2 Dynamic Frequency Divider 4 2.1.3 Injection-Locked Frequency Divider 6 2.1.4 Multi-Modulus Frequency Divider 9 2.1.5 Pulse Swallow Frequency Divider 11 2.2 Fractional-N Frequency Synthesis 13 2.2.1 Closed Loop Method 13 2.2.2 Open Loop Method 14 2.3 Prior Arts of Fractional Output Dividers 16 Chapter 3 DTC-Based Fractional Output Divider with 1-DTC Topology 21 3.1 The Proposed Fractional Output Divider with 1-DTC Topology 21 3.2 The Proposed DTC Background Calibration 24 3.3 Building Blocks 27 3.3.1 Digital-to-Time Converter (DTC) 27 3.3.2 Digital Multiplier 31 3.3.3 Comparator 33 3.3.4 Charge Pump 35 3.3.5 Pulse Generator 37 3.3.6 Multi-Modulus Divider 37 3.3.7 Programmable Divider 39 3.4 Simulation Results of the Proposed Fractional Output Divider 41 Chapter 4 Measurement Results of the Proposed Fractional Output Divider 46 4.1 Chip Micrograph 46 4.2 Measurement Setup 47 4.3 PCB Board Design 48 4.4 Measurement Results 49 4.4.1 Transient Waveform of the Output Signal 49 4.4.2 Phase Noise of the Output Signal 51 4.4.3 Spectrum of the Output Signal 55 4.4.4 Advanced Measurements 57 4.5 Summary 62 Chapter 5 Conclusion and Future Works 65 5.1 Conclusion 65 5.2 Future Works 65 References 66 | |
| dc.language.iso | en | |
| dc.title | 基於數位時間轉換器之開迴路小數除頻器的設計與實現 | zh_TW |
| dc.title | Design and Implementation of an Open-Loop Fractional Output Divider Based on Digital-to-Time Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 108-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),李泰成(Tai-Cheng Lee),陳信樹(Hsin-Shu Chen) | |
| dc.subject.keyword | 數位對時間轉換器,除頻器,展頻, | zh_TW |
| dc.subject.keyword | Digital-to-Time Converter,Frequency Divider,Spread Spectrum, | en |
| dc.relation.page | 69 | |
| dc.identifier.doi | 10.6342/NTU202000778 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2020-04-28 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-109-1.pdf 目前未授權公開取用 | 5.06 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。