使用65-nm CMOS製程製作之40-Gb/s背板通訊有線接收器

Abstract

在本論文中，實現了一種使用65-nm CMOS製程製作之40-Gb/s接收器，其中包含了幾種背板通訊有線接收器的主要電路──類比等化器、時脈資料回復電路以及解多工器。 這個類比等化器，是由兩級增益級和兩級濾波級所組成的，總共提供了最多14.9-dB的高頻增益補償，以及4.8-dB的直流增益。這將足夠地補償了Rogers板上5 cm的傳輸線，並且使電路有35-mV的輸入靈敏度。 接著是一個40-Gb/s的時脈資料回復電路，是由一個線性的相位偵測器以及一個不需要外灌參考時脈訊號的頻率偵測器所組成的。相位偵測器及頻率偵測器皆只需要資料訊號及壓控震盪器所產生的時脈訊號，即可自動偵測相位差以及頻率差。 接收器的最後一個部分是解多工器。如同大部分典型的架構，這個解多工器是由許多正反器所組成，並會取樣出所希望的輸出資料。此外，在這個設計中，40-Gb/s的資料將會被四分之一速度的時脈訊號取樣，因而解多工器會產生10-Gb/s的資料訊號。 此電路包含銲墊，共佔了1.1 × 1 mm^2，並由1.2-V的電源消耗了427 mW的功耗，且在輸入為2^31 – 1偽隨機二元序列時，達到位元誤碼率小於10^-12。

In this thesis, a 40-Gb/s receiver has been implemented in 65-nm CMOS technology, which composed of three critical components of a wireline backplane receiver – an analog equalizer, a clock and data recovery circuit (CDR), and a demultiplexer (DMUX). The analog equalizer consists of two gain stages and two filter stages, totally providing at most 14.9-dB boosting and 4.8-dB dc gain. It compensates sufficiently for the loss of the 5-cm channel on a Rogers board, and has a 35-mV input sensitivity. The following is a 40-Gb/s full-rate CDR, constructed with a linear phase detector (PD) and a frequency detector (FD) without an external reference clock. Both the PD and the FD operate only with the data signal and the clock signal from the voltage-controlled oscillator (VCO), and thus detect the phase error and the frequency error automatically. The last part of the receiver is a DMUX. Like most typical structures, this DMUX is implemented with flip-flops to sample the desired output data. Further, in this design, the 40-Gb/s data is sampled by the quarter-rate clock signal and thus the DMUX produces the 10-Gb/s data signal. This circuit occupies 1.1 × 1 mm^2 including pads, consumes 427 mW from a 1.2-V supply, and achieves BER < 10^-12 for 2^31 – 1 PRBS.