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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
dc.contributor.author | Hsing-Chih Chang Chien | en |
dc.contributor.author | 張簡幸枝 | zh_TW |
dc.date.accessioned | 2021-06-16T16:20:51Z | - |
dc.date.available | 2018-03-06 | |
dc.date.copyright | 2013-03-06 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-01-30 | |
dc.identifier.citation | [1] IBM ILOG CPLEX Optimizer, http://www01.ibm.com/software/integration/optimization/cplex-optimizer/.
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/63061 | - |
dc.description.abstract | 雙圖案微影技術近來備受注目且被認為是最適用於小於28奈米製程節點的方法。雙圖案微影技術將一個佈局分解成兩個佈局,並且用不同的光罩 (mask) 製造。除了傳統的類比電路設計條件之外,預先著色條件 (pre-coloring constraint) 也是重要的考量。預先著色條件是在分解圖案之前,將關鍵元件的圖案預先指定在同一光罩上以減消不匹配 (mismatch) 的效應。在本論文中,我們提出在擺置類比電路的同時考慮雙圖案微影技術並且盡可能的減少面積、線長以及圖案微影技術的圖案衝突 (conflict)。我們提出一個延展衝突關係圖 (extended conflict graph) 紀錄圖案的相互關係以及應用整數線性規劃決定每個元件的方向以及每個圖案的顏色以減少圖案衝突。此外,我們提出一個三階段的演算法以及考慮雙圖案微影的變換方式以得到較好的擺置結果。實驗結果顯示出我們提出的方法能夠有效地減少面積、線長以及圖案微影技術的圖案衝突。 | zh_TW |
dc.description.abstract | Double patterning lithography (DPL) is one of the most promising solutions for the 28nm technology node and beyond. The main idea of DPL is to decompose the layout into two sub-patterns and manufacture the layout by two masks. In addition to traditional analog design constraints, the pre-coloring constraint should also be considered, in which patterns of critical or sensitive modules have predefined masks before layout decomposition to reduce mismatches. In this thesis, we present the first work that considers DPL during analog placement and simultaneously minimizes area, wirelength, and DPL conflicts. We first propose an extended conflict graph (ECG) to represent the relation between patterns of analog modules and apply an integer linear programming (ILP) formulation to determine the orientation of each module and the color of each pattern for conflict minimization. Finally, we present a three-stage flow and DPL-aware perturbations to obtain desired solutions. Experimental results show that the proposed flow can effectively and efficiently reduce area, wirelength, and DPL conflicts. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T16:20:51Z (GMT). No. of bitstreams: 1 ntu-102-R99943170-1.pdf: 2364483 bytes, checksum: f993167b60dca3e9d7a34ee9322c8bc0 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | Acknowledgements iii
Abstract (Chinese) iv Abstract vi List of Tables x List of Figures xi Chapter 1. Introduction 1 1.1 Challenges for Lithography . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Double Patterning Lithography (DPL) . . . . . . . . . . . . . . . . . . . 4 1.3 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3.1 DPL-Compliant Design Tools . . . . . . . . . . . . . . . . . . . . . 7 1.3.2 Analog Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 2. Preliminaries 12 2.1 Review of CB-trees . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 Review of Analog Constraints . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Chapter 3. The DPL-Aware Analog Placement Algorithm 18 3.1 DPL Conict Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.1 Module Flipping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.1.2 Extended Conict Graph . . . . . . . . . . . . . . . . . . . . . . . 19 3.2 ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.1 Basic ILP Formulation . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.2.2 ILP Problem-Size Reduction . . . . . . . . . . . . . . . . . . . . . 26 3.2.2.1 Connected Component Computation . . . . . . . . . . . . 26 3.2.2.2 Two-Edge-Connected Component Computation . . . . . . 27 3.3 Perturbation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 General Perturbations . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.2 DPL-aware Perturbations . . . . . . . . . . . . . . . . . . . . . . . 30 3.4 The Three-Stage Placement Flow . . . . . . . . . . . . . . . . . . . . . . 31 Chapter 4. Experimental Results 38 Chapter 5. Conclusions and Future Work 46 Bibliography 50 Publication List 55 | |
dc.language.iso | en | |
dc.title | 考慮雙圖案微影技術之類比電路擺置 | zh_TW |
dc.title | Double Patterning Lithography-Aware Analog Placement | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭斯彥(Sy-Yen Kuo),李毅郎(Yih-Lang Li),陳宏明(Hung-Ming Chen) | |
dc.subject.keyword | 實體設計,類比電路擺置,對稱條件,雙圖案微影技術,佈局分割,可製造性, | zh_TW |
dc.subject.keyword | physical design,analog placement,double patterning lithography,layout decomposition,manufacturability, | en |
dc.relation.page | 55 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-01-30 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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