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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62846完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳信樹 | |
| dc.contributor.author | Sheng-Wei Lin | en |
| dc.contributor.author | 林昇緯 | zh_TW |
| dc.date.accessioned | 2021-06-16T16:12:16Z | - |
| dc.date.available | 2018-03-15 | |
| dc.date.copyright | 2013-03-15 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-02-18 | |
| dc.identifier.citation | [1] Z. Cao, S. Yan, and Y. Li, 'A 32 mW 1.25 GS/s 6b 2b/step SAR ADC in 0.13 um CMOS,' IEEE ISSCC Dig. Tech. Papers, Feb. 2008, pp. 542-543.
[2] H. Wei, C-H. Chan, U-F. Chio, S-W. Sin, S-P. U, R. Martins and F. Maloberti, 'A 0.024mm2 8b 400MS/s SAR ADC with 2b/cycle and Resistive DAC in 65nm CMOS,' IEEE ISSCC Dig. Tech. Papers, 2011. pp. 188-189. [3] K. Doris, E. Janssen, C. Nani, A. Zanikopoulos, and G. V. Weide, “A 480mW 2.6GS/s 10b 65nm CMOS Time-interleaved ADC with 48.5dB SNDR up to Nyquist,” IEEE ISSCC Dig. Tech. Papers, 2011. pp. 180-181. [4] Erkan Alpman, Hasnain Lakdawala1, L. Richard Carley, K. Soumyanath1 “A 1.1V 50mW 2.5GS/s 7b Time-Interleaved C-2C SAR ADC in 45nm LP Digital CMOS” IEEE ISSCC Dig. Tech. Papers, 2009. pp. 76-77. [5] S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3mW asynchronous ADC in 0.13-μm CMOS,” IEEE JSSC, vol. 41, no. 12, pp. 2669-2680, Dec 2006. [6] C. C. Liu, S. J. Chang, G. Y. Huang, and Y. Z. Lin, “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, pp. 731–740, Apr. 2010. [7]Tao Jiang, Wing Liu ; Zhong, F.Y. ; Zhong, C. ; Kangmin Hu ; Chiang, P.Y. “A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS” IEEE J. Solid-State Circuits, vol. 47, pp. 2444–2453, Oct. 2012. [8] Yoshioka, K. Shikata, A., Sekimoto, R. , Kuroda, T. , Ishikuro, H. “An 8bit 0.35-0.8V 0.5-30MS/s 2bit/step SAR ADC with Wide Range Threshold Configuring Comparator,” in ESSCIRC Nov. 2012. [9] G. Van der Plas, S. Decoutere, and S. Donnay, “A 0.16 pJ/conversionstep 2.5 mW 1.25 GS/s 4 b ADC in a 90 nm digital CMOS process,” in ISSCC Dig. Tech. Papers, Feb. 2006. [10] Bernhard Wicht, Thomas Nirschl, and Doris Schmitt-Landsiedel, “Yield and Speed Optimization of a Latch-Type Voltage Sense Amplifier” in IEEE J. Solid-State Circuits, vol. 39, no.7, July. 2004 [11] Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, “A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs,” in IEEE A-SSCC, pp. 269-272, Nov. 2008. [12] W. Y. Pang, C. S. Wang, Y. K. Chang, N. K. Chou, and C. K. Wang, “A 10-bit 500-KS/s low power SAR ADC with splitting capacitor for bio-medical applications,” in Proc. IEEE A-SSCC, 2009, pp. 149–152. [13] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U, R. P. Martins, and F. Maloberti, “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111–1121, Jun. 2010. [14] C. H. Kuo and C. E. Hsieh, “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” in Proc. IEEE ESSCIRC, 2011, pp. 475–478. [15] A.M. Abo, and P.R. Gray, “A 1.5-V 10-bit 14.3-MS/s CMOS pipeline analog-to- digital converter,” IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, May. 1999. [16] Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, ” A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS” in IEEE Dig. Symp. VLSI Circuits, Honolulu, Hawaii, pp92-93, June 2012. [17] J. Yang, T. L. Naing, and R. W. Brodersen, “A 1 GS/s 6 Bit 6.7 Mw successive approximationADC using asynchronous processing,” IEEE J. Solid-State Circuits, vol. 45, no. 8, pp. 1469–1478, Aug. 2010. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62846 | - |
| dc.description.abstract | 以40奈米CMOS製程實現的一個單通道非同步六位元每秒十二億次的連續漸近式類比數位轉換器被提出來。
此設計中，使用了一次兩位元轉換的技術。比較於先前一次兩位元轉換的連續漸近式類比數位轉換器，此架只用了三排電容陣列，以節省硬體及功耗。 這本作品，以單通道達到每秒十二億次的取樣頻率。為了降低比較器的偏移電壓，本設計使用了基板端電容的前景校正方式。 此晶片量測結果，使用了不同的電壓以測試類比數位轉換器最大的速度效能。此連續漸近式的類比數位轉換器在供應電壓為1伏時，可達到每秒十億次取樣，功耗為4.18毫瓦。操作在1.1伏時，可達每秒十二億次取樣功耗為6.24毫瓦。取樣頻率為每秒十億次時，最高的SNDR可達34.75dB。取樣頻率為每秒十二億次時，最高的SNDR可達34.66dB。全晶片的面積大小為0.39 mm2，而主動電路所占面積只有0.016 mm2。 | zh_TW |
| dc.description.abstract | A single channel, asynchronous, 6-bit successive approximation ADC with 1.2GS/s, in 40nm CMOS technology is proposed.
In this design, the 2-bit/cycle technique is used. Compared with the previously 2-bit/cycle, this architecture uses just three capacitor arrays to reduce the hardware and power consumption. In this work, single-channel, 1.2GS/s is achieved. This design uses the body capacitance foreground calibration in order to reduce the comparator offset voltage. The measurements are performed with different supplies, in order to test the chips’ maximum performance of conversion rate. The SAR ADC can reach 1GS/s with a 1V supply, consuming 4.08mW. And it reaches 1.2GS/s with a 1.1 supply voltage, consuming 6.2mW. At 1GS/s, the peak signal to noise and distortion ratio is 34.75dB. When the sampling rate is increased to 1.2GS/s, the peak signal to noise and distortion ratio is 34.66dB. The ADC occupies an active area of 0.016 mm2, and whole chip with pads occupies 0.39 mm2. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T16:12:16Z (GMT). No. of bitstreams: 1 ntu-102-R99943113-1.pdf: 2022558 bytes, checksum: ddcaa17acd5c97bf746a2c539863930c (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | Contents
摘要 I ABSTRACT II CONTENT III List of Figures VII List of Tables XII Chapter 1 INTRODUCTION 1 1.1 Motivation 1 1.2 Thesis Organization 2 Chapter 2 FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTER 3 2.1 Introduction 3 2.2 Performance Metrics 3 2.2.1 Offset and Gain Error 3 2.2.2 Differential and Integral Nonlinearity (DNL, and INL) 4 2.2.3 Signal-to-Noise Ratio (SNR) 5 2.2.4 Total Harmonic Distortion (THD) 6 2.2.5 Spurious-Free Dynamic Range (SFDR) 7 2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) 7 2.2.7 Effective Number of Bits (ENOB) 7 2.2.8 Figure of Merit (FoM) 8 2.3 Architecture of Analog-to-Digital Converters 8 2.3.1 Flash ADC Architecture 9 2.3.2 Two-step ADC Architecture 10 2.3.3 Pipelined ADC Architecture 11 2.3.4 Successive-approximation ADC Architecture 13 2.4 Summary 14 Chapter 3 PROPOSED 2-BIT/CYCLE ARCHITECTURE AND COMPARATOR OFFSET CALIBRATION CIRCUITS 16 3.1 Introduction 16 3.2 2-bit/cycle SAR ADC 17 3.2.1 Traditional 2-bit/cycle SAR ADC 17 3.2.2 Resistive DAC-based 2-bit/cycle SAR ADC 19 3.2.3 2-bit/cycle SAR ADC with wide range threshold configuring comparator ……………………………………………………………………….20 3.2.4 Proposed 2-bit/cycle architecture 22 3.3 Comparator offset calibration circuits 24 3.3.1 Digital Background Offset Calibration 24 3.3.2 A Voltage Controlled Capacitance Offset Calibration 25 3.3.3 The Offset Calibration of body biasing technique 26 3.3.4 Proposed Foreground Offset Calibration 26 3.4 Summary 28 Chapter 4 CIRCUIT IMPLEMENTATION AND SIMULATION RESULTS 29 4.1 Introduction 29 4.2 Building Blocks and Circuit Implementation 29 4.2.1 Comparator 30 4.2.2 Calibration Cirsuit 34 4.2.3 Capacitor array 39 4.2.4 Bootstrap Circuits 40 4.2.5 Digital controller 42 4.2.6 Clock Generator 48 4.3 Overall ADC Simulation Results 50 4.3.1 Algorithm Simulation 50 4.3.2 Transistor Level Simulation 51 4.4 Summary 53 Chapter 5 MEASUREMENT RESULTS 54 5.1 Introduction 54 5.2 Measurement Setup 54 5.3 PCB design 56 5.4 Floor Plan and Layout 61 5.5 Measurement Results 63 5.5.1 Static Performance 64 5.5.2 Dynamic Performance 67 5.6 Summary 73 Chapter 6 CONCLUSIONS 74 Bibliography 75 | |
| dc.language.iso | zh-TW | |
| dc.subject | 類比數位轉換器 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 高速 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 一次兩位元轉換 | zh_TW |
| dc.subject | Analog to digital converter | en |
| dc.subject | SAR | en |
| dc.subject | high speed | en |
| dc.subject | low power | en |
| dc.subject | 2-bit/cycle | en |
| dc.title | 一個單通道六位元一次兩位元轉換每秒十二億次取樣的連續漸近式類比數位轉換器 | zh_TW |
| dc.title | A Single-channel, 1.2GS/s, 6-bit, 2-bit/cycle SAR ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 郭建宏,盧亦璋 | |
| dc.subject.keyword | 類比數位轉換器,連續漸進式,高速,低功率,一次兩位元轉換, | zh_TW |
| dc.subject.keyword | Analog to digital converter,SAR,high speed,low power,2-bit/cycle, | en |
| dc.relation.page | 77 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-02-18 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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