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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 鄭振牟 | |
dc.contributor.author | Yun-An Chang | en |
dc.contributor.author | 張運安 | zh_TW |
dc.date.accessioned | 2021-06-16T13:43:55Z | - |
dc.date.available | 2013-07-18 | |
dc.date.copyright | 2013-07-18 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-07-10 | |
dc.identifier.citation | Bibliography
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62366 | - |
dc.description.abstract | Bilinear pairings on elliptic curves have many applications in both constructive cryptography and cryptanalysis. Pairing computation is much more complicated compared to that of other popular public-key cryptosystems. Efficient implementation of cryptographic pairing has thus received increasing interest, both from software and hardware approaches, pursuing higher speed or, in the cases of hardware implementation, smaller time-area product. In
this paper, we will present the design and implementation of a programmable cryptographic coprocessor that supports various pairings at 128-bit security level. Unlike the general architecture, our design is optimized for carrying out pairing computation over fields of large characteristics. As a result, our design stays competitive even compared with specialized implementations in terms of time-area product. For example, we will show that by using heterogeneous arithmetic units, we can achieve a significant speed-up for pairing computation over Barreto-Naehrig curves, resulting in an implementation that achieves a latency of 3.58 ms with a gate count of around 156K. To the best of our knowledge, this is the smallest time-area product achieved among all implementations of optimal ate pairing using application-specific integrated circuits. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T13:43:55Z (GMT). No. of bitstreams: 1 ntu-102-R00921032-1.pdf: 2137367 bytes, checksum: ff41a4ca6a9aa70dffae55fab082ccaf (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | Contents
致謝i 中文摘要iii Abstract v 1 Introduction 1 2 Background 3 2.1 Bilinear Pairings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Barreto-Naehrig Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.3 Computing Optimal Ate Pairing . . . . . . . . . . . . . . . . . . . . . . 4 3 Going Heterogeneous 7 4 The Design 9 4.1 Bluespec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 Full Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 Add-only Arithmetic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.4 Processor Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 Performance Evaluation 15 5.1 Tuning the Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 Performance Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 Conclusion 19 Bibliography 21 | |
dc.language.iso | en | |
dc.title | Optimal Ate pairing 的硬體實作 | zh_TW |
dc.title | A hardware implementation of the optimal Ate pairing on a 256-bit Barreto-Naehrig curve | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 楊柏因,陳君明 | |
dc.subject.keyword | Optimal Ate pairing,Barreto-Naehrig 曲線,特定應用積體電路實作, | zh_TW |
dc.subject.keyword | Optimal Ate pairing,Barreto-Naehrig Curve,ASIC implementation, | en |
dc.relation.page | 23 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-07-10 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
顯示於系所單位: | 電機工程學系 |
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