請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62291完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 吳宗霖(Tzong-Lin Wu) | |
| dc.contributor.author | Yu-Jen Chang | en |
| dc.contributor.author | 張佑任 | zh_TW |
| dc.date.accessioned | 2021-06-16T13:39:03Z | - |
| dc.date.available | 2016-07-25 | |
| dc.date.copyright | 2013-07-25 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-07-15 | |
| dc.identifier.citation | [1] S. Borkar, “Design challenges of technology scaling,” IEEE Micro, vol. 19, no. 4, pp. 23–29, July-Aug. 1999.
[2] G. Moore, 'Cramming more components onto integrated circuits,' Electron., vol. 38, no. 8, pp. 114-117, 19 Apr. 1965. [3] C. A. Mack, “Fifty years of moore’s law,” IEEE Trans. Semicond. Manuf., vol. 24, no. 2, pp. 202–207, May 2011. [4] F. Schwierz, 'Graphene transistors,' Nature Nanotechnol., 5, pp. 487-496, May 2010. [5] International Roadmap for Semiconductors (ITRS), 2012 Update. http://www.itrs.net. [6] R. R. Tummala, “SOP: what is it and why? a new microsystem-integration technology paradigm-moore’s law for system integration of miniaturized convergent systems of the next decade,” IEEE Trans. Adv. Packag., vol. 27, no. 2, pp. 241–249, May 2004. [7] R. R. Tummala, “Packaging: past, present and future,” in IEEE Int. Conf. Electron. Packag. Technol., 2005, pp. 3–7. [8] E. Beyne, “The rise of the 3rd dimension for system integration,” in IEEE Int. Technol. Conf., 2006, pp. 1–5. [9] W. R. Davis, J. Wilson, S. Mick, J. Xu, H. Hua, C. Mineo, A. M. Sule, M. Steer, and P. D. Franzon, “Demystifying 3D ICs: the pros and cons of going vertical,” IEEE Des. Test Comput., vol. 22, no. 6, pp. 498 – 510, Dec. 2005. [10] A. W. Topol, D. C. La Tulipe, Jr., L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM J. Res. Develop., vol. 50, no. 4/5, pp. 491–506, July–Sep. 2006. [11] M. Motoyoshi, “Through-silicon via (TSV),” Proc. IEEE, vol. 97, no. 1, pp. 43-48, Jan. 2009 [12] M. Rimskog and T. Bauer, “High density through silicon via (TSV),” in IEEE Symp. Des., Test, Integr. Packag. MEMS/MOEMS, 2008, pp. 105–108. [13] M. Swaminathan, and A. Ege Engin, Power Integrity Modeling and Design for Semiconductors and Systems, Prentice Hall, 2008. [14] K. Kim, C. Hwang, K. Koo, J. Cho, H. Kim, J. Kim, J. Lee, H.-D. Lee, K.-W. Park, and J. S. Pak, “Modeling and analysis of a power distribution network in TSV-based 3-D memory IC including P/G TSVs, on-chip decoupling capacitors, and silicon substrate effects,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 2, no. 12, pp. 2057 –2070, Dec. 2012. [15] G. Huang, M. Bakir, A. Naeemi, H. Chen, and J. D. Meindl, “Power delivery for 3D chip stacks: physical modeling and design implication,” in IEEE Elect. Perform. Electron. Packag., 2007 IEEE, 2007, pp. 205 –208. [16] G. Huang, M. S. Bakir, A. Naeemi, and J. D. Meindl, “Power delivery for 3-D chip stacks: physical modeling and design implication,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 2, no. 5, pp. 852 –859, May 2012. [17] J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, “PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 208 –219, Feb. 2011. [18] X. Hu, P. Du, J. F. Buckwalter, and C.-K. Cheng, “Modeling and analysis of power distribution networks in 3-D ICs,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 2, pp. 354 –366, Feb. 2013. [19] W. Ahmad, L.-R. Zheng, Q. Chen, and H. Tenhunen, “Peak-to-peak ground noise on a power distribution TSV pair as a function of rise time in 3-D stack of dies interconnected through TSVs,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 196 –207, Feb. 2011. [20] H. Y. Cheng, “Design of through-silicon via assignments for minimizing simultaneous switching noise in 3-D IC,” M.S. thesis, University of Taiwan, Taipei, ON, Taiwan, 2011. [21] Z. Xu, Q. Wu, H. He, and J. J.-Q. Lu, “Electromagnetic-simulation program with integrated circuit emphasis modeling, analysis, and design of 3-D power delivery,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 3, no. 4, pp. 641–652, Apr. 2013. [22] K. Kang, L. Nan, S. C. Rustagi, K. Mouthaan, J. Shi, R. Kumar, W.-Y. Yin, and L.-W. Li, “A wideband scalable and SPICE-compatible model for on-chip interconnects up to 110 GHz,” IEEE Trans. Microw. Theory Tech., vol. 56, no. 4, pp. 942 –951, Apr. 2008. [23] S.-P. Sim, S. Krishnan, D. M. Petranovic, N. D. Arora, K. Lee, and C. Y. Yang, “A unified RLC model for high-speed on-chip interconnects,” IEEE Trans. Electron Devices, vol. 50, no. 6, pp. 1501 – 1510, Jun. 2003. [24] D. Jiao, M. Mazumder, S. Chakravarty, C. Dai, M. J. Kobrinsky, M. C. Harmes, and S. List, “A novel technique for full-wave modeling of large-scale three-dimensional high-speed on/off-chip interconnect structures,” in IEEE Int. Conf. Simulation Semicond. Processes Devices, 2003, pp. 39–42. [25] P. J. Restle, A. E. Ruehli, S. G. Walker, and G. Papadopoulos, “Full-wave PEEC time-domain method for the modeling of on-chip interconnects,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 20, no. 7, pp. 877–886, July 2001. [26] M. J. Kobrinsky, S. Chakravarty, D. Jiao, M. Harmes, S. List, and M. Mazumder, “Experimental validation of crosstalk simulations for on-chip interconnects at high frequencies using S-parameters,” in IEEE Elect. Perform. Electron. Packag., 2003, pp. 329–332. [27] C. Ryu, J. Lee, H. Lee, K. Lee, T. Oh, and J. Kim, “High frequency electrical model of through wafer via for 3-D stacked chip packaging,” in IEEE Electron. Systeminteg. Technol. Conf., 2006, pp. 215–220. [28] I. Ndip, B. Curran, K. Lobbicke, S. Guttowski, H. Reichl, K.-D Lang, and H. Henke, “High-frequency modeling of TSVs for 3-D chip integration and silicon interposers considering skin-effect, dielectric quasi-TEM and slow-wave modes,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 10, pp. 1627-1641, Oct. 2011. [29] T.-Y. Cheng, C.-D. Wang, Y.-P. Chiou, and T.-L. Wu, “A new model for through-silicon vias on 3-D IC using conformal mapping method,” IEEE Microw. Wireless Compon. Lett.,vol. 21, no. 6, pp. 303-305, Jun. 2012. [30] T.-Y. Cheng, “Power delivery network modeling methodologies and automation for three-dimensional integrated circuit (3-D IC),” M.S. thesis, University of Taiwan, ON, Taiwan, 2012. [31] C.-D. Wang, Y.-J. Chang, Y.-C. Lu, P.-S. Chen, W.-C. Lo, Y.-P. Chiou, T.-L. Wu, 'ABF-Based TSV arrays with improved signal integrity on 3-D IC/interposers: equivalent models and experiments,' IEEE. Trans. Compon. Packag. Manuf. Technol., accepted for publication [32] K. J. Han, M. Swaminathan, and T. Bandyopadhyay, “Electromagnetic modeling of through-silicon via (TSV) interconnections using cylindrical modal basis functions,” IEEE Trans. Adv. Packag., vol. 33, no. 4, pp. 804-817, Nov. 2010. [33] A. E. Engin and S. R. Narasimhan, “Modeling of crosstalk in through silicon vias,” IEEE Trans. Electromagn. Compat., vol. 55, no. 1, pp. 149–158, Feb. 2013. [34] H. A. Wheeler, “Formulas for the skin effect,” Proc. IRE, vol. 30, no. 9, pp. 412 – 424, Sep. 1942. [35] S. Kim and D. P. Neikirk, “Compact equivalent circuit model for the skin effect,” in IEEE MTT-S Int. Microw. Symp. Dig., 1996, vol. 3, pp. 1815 –1818. [36] C.-S. Yen, Z. Fazarinc, and R. L. Wheeler, “Time-domain skin-effect model for transient analysis of lossy transmission lines,” Proc. IEEE, vol. 70, no. 7, pp. 750 – 757, July 1982. [37] A. E. Ruehli, “Inductance calculations in a complex integrated circuit environment,” IBM J. Res. Develop., vol. 16, no. 5, pp. 470 –481, Sep. 1972. [38] P. Silvester, “Modal network theory of skin effect in flat conductors,” Proc. IEEE, vol. 54, no. 9, pp. 1147–1151, Sep. 1966. [39] A. Ege Engin, W. Mathis, W. John, G. Sommer, and H. Reichl, “Closed-form network representations of frequency-dependent RLGC parameters,” Int. J. Circuit Theory Applicat., vol. 33, no. 6, pp. 463–485, Nov. 2005. [40] V. Kluyskens and B. Dehez, “Comparison between models predicting the evolution of the electrical impedance with frequency,” Int. J. Circuit Theory Applicat., vol. 39, no. 9, pp. 973–982, Sep. 2011. [41] R. K. Ulrich and W. D. Brown, Advanced Electronic Packaging. New York: Wiley, 2006. [42] T. Jiang and S. Luo, “3D integration-present and future,” in IEEE Electron. Packag. Technol.Conf., Dec. 2008, pp. 373–378. [43] A. Yu, J. H. Lau, S. W. Ho, A. Kumar, W. Y. Hnin, D.-Q. Yu, M. C. Jong, V. Kripesh, D. Pinjala, and D.-L. Kwong, “Study of 15 μm pitch solder microbumps for 3D IC integration,” in IEEE Electron. Compon. Technol. Conf., May 2009, pp. 6–10. [44] U. Kang, H.-J. Chung, S. Heo, D.-H. Park, H. Lee, J.-H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, D. Kwon, J.-W. Lee, H.-S. Joo, W.-S. Kim, D. H. Jang, N. S. Kim, J.-H. Choi, T.-G. Chung, J.-H. Yoo, J.-S. Choi, C. Kim, and Y.-H. Jun, “8 Gb 3-D DDR3 DRAM using through-silicon-via technology,” IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 111–119, Jan. 2010. [45] Henry D. et al, “Via first technology development based on high aspect ratio trenches filled with doped polysilicon”, in IEEE Electron. Compon. Technol. Conf., Reno, NV, May 2007, pp. 830 – 835. [46] H. Li, C. Xu, N. Srivastava, and K. Banerjee, “Carbon nanomaterials for next-generation interconnects and passives: physics, status, and prospects,” IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1799 –1821, Sep. 2009. [47] W.-S. Zhao, W.-Y. Yin, and Y.-X. Guo, “Electromagnetic compatibility-oriented study on through silicon single-walled carbon nanotube bundle via (TS-SWCNTBV) arrays,” IEEE Trans. Electromagn. Compat., vol. 54, no. 1, pp. 149–157, Feb. 2012. [48] Z. Xu and J.-Q. Lu, “High-speed design and broadband modeling of through-strata-vias (TSVs) in 3D integration,” IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 154–162, Feb. 2011. [49] J. H. Lau, “TSV manufacturing yield and hidden costs for 3D IC integration,” in IEEE Electron. Compon. Technol. Conf., 2010, pp. 1031–1042. [50] J. H. Lau, “Evolution, challenge, and outlook of TSV, 3D IC integration and 3d silicon integration,” in IEEE Int. Symp. Adv. Packag. Mater., Oct. 2011, pp. 462–488. [51] W.-C. Lo, Y.-H. Chen, J.-D. Ko, T.-Y. Kuo, Y.-C. Shih, and S.-T. Lu, “An innovative chip-to-wafer and wafer-to-wafer stacking”, in IEEE Electron. Compon. Technol. Conf., San Diego, CA, US, May-Jun. 2006, pp. 6. [52] T.-Y. Kuo, S.-M. Chang, Y.-C. Shih, C.-W. Chiang, C.-K. Hsu, C.-K. Lee, C.-T. Lin, Y.-H. Chen, and W.-C. Lo, “Reliability tests for a three dimensional chip stacking structure with through silicon via connections and low cost,” in IEEE Electron. Compon. Technol. Conf., Florida, USA, May. 2008, pp. 853-858. [53] C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base,” in IEEE Int. Test Conf., Sep. 2011, pp. 1–10. [54] M. Popovich, A. V. Mezhiha, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Springer Science + Business Media, 2008. [55] C. R. Paul, Analysis of Multiconductor Transmission Lines. New York: Wiley, 1994. [56] C. L. Holloway and E. F. Kuester, “DC internal inductance for a conductor of rectangular cross section,” IEEE Trans. Electromagn. Compat., vol. 51, no. 2, pp. 338 –344, May 2009. [57] R. De Smedt, “Addition to ldquo;DC internal inductance for a conductor of rectangular cross section rdquo;,” IEEE Trans. Electromagn. Compat., vol. 51, no. 3, pp. 875 –876, Aug. 2009. [58] W. H. Schilders , H. A. van der Vorst, and J. Rommes, Model Order Reduction: Theory, Research Aspects and Applications. Berlin, Germany: Springer-Verlag, 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62291 | - |
| dc.description.abstract | 為了滿足日漸提高的高性能消費性電子產品的需求，半導體產業在過去四十年來有飛躍性的進步，摩爾定律也一直被奉為圭臬而持續遵循。不過，由於今日電晶體大小已相當接近物理的極限，想要繼續縮小電晶體尺寸同時維持低成本已變得相當困難，造成此一定律變得難以遵循。為了突破此一困境，最近幾年許多可能的解決方案紛紛被提出。其中使用直通矽晶孔柱的三維積體電路由於有較低的功耗、較小的電阻壓降和較高的傳輸速度，因而成為最有可能繼續摩爾定律甚至超越摩爾定律的解決方案。
雖然使用直通矽晶孔柱的三維積體電路被寄予厚望且發展蓬勃，此一技術仍有許多挑戰及困難有待克服，像是電氣特性議題、熱流傳導議題、成本議題．．．等。在電氣特性議題中，電源供應網路的設計是相當關鍵性的問題。在沒有適當設計的情況下，一個系統可能會因而效能降低甚至失去應有的功能。而想要適當的設計它，一個正確且有效率的電源供應網路模型是必要的。因此，本文重視如何建立正確的三維積體電路中電源供應網路模型以及如何改善其模擬效率，並同時提出適當的解決方案。 對於正確性這一點，本文提出一個階梯狀電路的建置流程，用此一電路來正確地描述三維積體電路中電源供應網路之集膚效應。和傳統常用的方法相比，此一電路不但頻域模擬正確性較高而且可以直接進行時域的模擬，也不會有任何潛在的被動性和因果性的電路問題，因此使用此電路分析電源供應網路也會更有效率。更重要的是，此一電路模型可以由結構的物理尺寸及材料特性直接獲得，不須額外使用電氣特性萃取的軟體，因此對於自動化電路建置流程有很大的幫助。 為了改善所建立的電源供應網路模型之模擬效率，本文提出一套簡化模型的方法來化簡此一相當複雜的電源供應網路模型。此一方法是依據基本的串、並聯及單位元的概念建立。運用此化簡方法可以顯著地減少模型中所需的電路元件數，因此模擬時間可以縮短。更重要的是，簡化的模型在時域和頻域的正確性依舊相當高。 | zh_TW |
| dc.description.abstract | With the demand of the high-performance consumer electronics, the semiconductor industry has progressed dramatically in the past 40 years, and Moore’s law has guided the development of the entire semiconductor industry. However, as the size of transistors approaches the physical limit, this law is much more difficult to be tenable due to the difficulties in shrinking the gate length at the same time remaining low-cost. To overcome this obstacle, many possible solutions have been proposed. Among them, three-dimensional integrated circuit (3-D IC) with through silicon vias (TSVs) has the advantages of lower power consumption, smaller IR drop, and higher transmission rate capability. Therefore, it is very likely to become the major method to continue Moore’s law or to become “more than Moore”.
Although 3-D IC with TSVs has great potential, there are still many challenges needed to be overcome such as electrical-property issues, thermal issues, cost issue, and so on. Among electrical-property issues, the design of power delivery network (PDN) is one of the most critical problems. A system can degrade or even malfunction without a good design of PDN. To facilitate it, a not only accurate but also efficient model of PDN is essential. Therefore, this thesis focuses on how to establish an accurate model for PDN in 3-D IC and how to improve the simulation efficiency. In terms of accuracy, a ladder-circuit-model-constructing methodology is proposed to accurately characterize the non-negligible skin effect of PDN in the 3-D IC. Compared with the conventional skin effect model, the accuracy of this model is much higher. In addition, this model can be directly used in time-domain simulation without any potential passivity and causality problems, which can also make the analysis of the PDN more efficient. Most importantly, this model can be constructed from its physical dimensions and material properties without any help of electrical-parameter extraction tools, which makes the automation of the methodology straightforward. To improve the efficiency of the established model of PDN in 3-D IC, a simplification methodology for the rather complex PDN model in 3-D IC, based on the basic serial formulas, shunt formulas, and unit-cell concept, is proposed. This simplification method can significantly reduce the number of the circuit elements in the model, which makes the simulation time much shorter, but the accuracy is still good enough both in frequency domain and in time domain. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T13:39:03Z (GMT). No. of bitstreams: 1 ntu-102-R00942014-1.pdf: 7487711 bytes, checksum: 2c3eb1df57b3556834a40643dc925e74 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 國立台灣大學碩士學位論文口試委員會審定書 #
誌謝 i 中文摘要 iii ABSTRACT v CONTENTS vii LIST OF FIGURES xi LIST OF TABLES xvii ACRONYMS xix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Literature Survey 3 1.3 Contributions 6 1.4 Thesis Organization 7 Chapter 2 3-D IC Technology and Circuit Modeling 9 2.1 3-D Stacking Technology 9 2.1.1 Wire Bonding 9 2.1.2 Microbump with Side Metals 10 2.2 Through Silicon Via (TSV) 11 2.3 3-D IC Configuration 15 2.4 Circuit Model of PDN in 3-D IC 17 2.4.1 Through Silicon Via (TSV) 18 2.4.2 Bump 21 2.4.3 Power/Ground Grid 22 2.4.4 Interaction between Grids and Silicon Substrate 25 Chapter 3 Improved Electrical Model for Skin Effect of PDN in 3-D IC 29 3.1 Conventional Method 30 3.2 Proposed Methodology to Model Skin Effect 33 3.2.1 Basic Theory of Ladder Model 34 3.2.2 Analytic Formulas of Equivalent Circuit Elements 38 3.2.3 Order Decision of Ladder Model 49 3.2.4 Construction Flow of Equivalent Circuit Model 56 3.3 Application to PDN in 3-D IC 57 3.3.1 Physical Structure 57 3.3.2 Equivalent Circuit Model 60 3.3.3 Frequency-Domain Simulation Results 61 3.3.4 Time-Domain Simulation Results 66 3.3.5 Comparisons 72 3.4 Summary 74 Chapter 4 Circuit Model Simplification of PDN in 3-D IC 75 4.1 Proposed Simplification Methodology 76 4.1.1 Unit Cell Simplification Method for Power/Ground Grids 76 4.1.2 Non-uniform Segmentation for Power/Ground Grids 93 4.1.3 Connection Method with TSVs and Bumps 101 4.1.4 Construction Flow of Simplified Circuit Model 103 4.2 Application to PDN in 3-D IC 104 4.2.1 Physical Structure and Circuit Modeling 104 4.2.2 Simulation Results 106 4.2.3 Efficiency Comparisons 115 4.3 Summary 118 Chapter 5 Conclusions 119 ACKNOWLEDGEMENT 121 REFERENCE 122 PUBLICATION LIST 131 | |
| dc.language.iso | en | |
| dc.subject | 電路模型化簡 | zh_TW |
| dc.subject | 等效電路模型 | zh_TW |
| dc.subject | 電源供應網路 | zh_TW |
| dc.subject | 電源完整度 | zh_TW |
| dc.subject | 集膚效應 | zh_TW |
| dc.subject | 三維積體電路 | zh_TW |
| dc.subject | 時域模擬 | zh_TW |
| dc.subject | skin effect | en |
| dc.subject | power integrity | en |
| dc.subject | circuit model simplification | en |
| dc.subject | equivalent circuit model | en |
| dc.subject | power delivery network | en |
| dc.subject | time-domain simulation | en |
| dc.subject | three-dimensional integrated circuit | en |
| dc.title | 三維積體電路電源供應網路的高效率時域模型建置方法 | zh_TW |
| dc.title | An Efficient Time-Domain Power-Delivery-Network Modeling Methodology for Three-Dimensional Integrated Circuit (3-D IC) | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 吳瑞北(Ruey-Beei Wu),邱奕鵬(Yih-Peng Chiou),盧奕璋(Yi-Chang Lu),莊皓翔(Hao-Hsiang Chuang) | |
| dc.subject.keyword | 電路模型化簡,等效電路模型,電源供應網路,電源完整度,集膚效應,三維積體電路,時域模擬, | zh_TW |
| dc.subject.keyword | circuit model simplification,equivalent circuit model,power delivery network,power integrity,skin effect,three-dimensional integrated circuit,time-domain simulation, | en |
| dc.relation.page | 131 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-07-16 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| 顯示於系所單位： | 電信工程學研究所 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-102-1.pdf 未授權公開取用 | 7.31 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。