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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國 | |
dc.contributor.author | Tzu-Hao Chiang | en |
dc.contributor.author | 江子豪 | zh_TW |
dc.date.accessioned | 2021-06-16T13:33:04Z | - |
dc.date.available | 2020-07-22 | |
dc.date.copyright | 2020-07-22 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-06-17 | |
dc.identifier.citation | M. Y. Doghish and F. D. Ho, “A comprehensive analytical model for metal-insulator-semiconductor (MIS) devices: a solar cell application,” IEEE Trans. Electron Devices, vol. 40, no. 8, pp. 1446-1454, Aug. 1993, doi:10.1109/16.223704.
M. A. Green, R. B. Godfrey, “MIS solar cell-general theory and new experimental results for silicon,” Appl. Phys. Lett., vol. 29, no. 9, pp. 610, 1976, doi: 10.1063/1.89161. C. W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, 'A novel photodetector using MOS tunneling structures,' IEEE Electron Device Letters, vol. 21, no. 6, pp. 307-309, June 2000. doi: 10.1109/55.843159. Y.-H. Shih and J.-G. Hwu, “An on-chip temperature sensor by utilizing a MOS tunneling diode,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 299-301, Jun., 2001, doi: 10.1109/55.924848. T.-Y. Chen and J.-G. Hwu, “Two states phenomenon in the current behavior of metal-oxide-semiconductor capacitor structure with ultra-thin SiO2,” Appl. Phys. Lett., vol. 101, no. 7, pp. 073506-1073506-4, Aug., 2012, doi: 10.1063/1.4746284. C.-S. Liao and J.-G. Hwu, 'Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,' IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2864-2870, July 2016. doi: 10.1109/TED.2016.2565688. G. E. Moore, 'Cramming More Components Onto Integrated Circuits,' Proceedings of the IEEE, vol. 86, no. 1, pp. 82-85, Jan. 1998. doi: 10.1109/JPROC.1998.658762. A. M. Ionescu, L. D. Michielis, N. Dagtekin, G. Salvatore, J. Cao, A. Rusu, and S. Bartsch, 'Ultra low power: Emerging devices and their benefits for integrated circuits,' International Electron Devices Meeting, Washington, DC, pp. 16.1.1-16.1.4, 2011. doi: 10.1109/IEDM.2011.6131563. K. Bernstein, R. K. Cavin, W. Porod, A. Seabaugh, and J. Welser, 'Device and Architecture Outlook for Beyond CMOS Switches,' Proceedings of the IEEE, vol. 98, no. 12, pp. 2169-2184, Dec. 2010. doi: 10.1109/JPROC.2010.2066530. N. Abele, R. Fritschi, K. Boucart, F. Casset, P. Ancey, and A. M. Ionescu, 'Suspended-gate MOSFET: bringing new MEMS functionality into solid-state MOS transistor,' IEEE International Electron Devices Meeting, IEDM Technical Digest., Washington, DC, pp. 479-481, Apr. 2006. doi: 10.1109/IEDM.2005.1609384. A. Rusu, G. A. Salvatore, D. Jiménez, and A. M. Ionescu, 'Metal-Ferroelectric-Meta-Oxide-semiconductor field effect transistor with sub-60mV/decade subthreshold swing and internal voltage amplification,' International Electron Devices Meeting, San Francisco, CA, pp. 16.3.1-16.3.4, Dec. 2010. doi: 10.1109/IEDM.2010.5703374. K. Gopalakrishnan, P. B. Griffin and J. D. Plummer, “I-MOS: a novel semiconductor device with a subthreshold slope lower than kT/q,” Digest. International Electron Devices Meeting,, San Francisco, CA, USA, 2002, pp. 289-292. doi: 10.1109/IEDM.2002.1175835. W. Y. Choi, B. Park, J. D. Lee and T. K. Liu, “Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, Aug. 2007. doi: 10.1109/LED.2007.901273. K. H. Lee, H. E. Dirani, P. Fonteneau, M. Bawedin, S. Sato and S. Cristoloveanu, “Sharp switching, hysteresis-free characteristics of Z2-FET for fast logic applications,” 2018 48th European Solid-State Device Research Conference (ESSDERC), Dresden, 2018, pp. 74-77. doi: 10.1109/ESSDERC.2018.8486915. C.-S. Liao and J.-G. Hwu, 'Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor,' IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 2061-2065, June 2015. doi: 10.1109/TED.2015.2424245. C.-F. Yang, B.-J. Chen, W.-C. Chen, K.-W. Lin, and J.-G. Hwu, 'Gate Oxide Local Thinning Mechanism-Induced Sub-60 mV/Decade Subthreshold Swing on Charge-Coupled MIS(p) Tunnel Transistor,' IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 279-285, Jan. 2019. doi: 10.1109/TED.2018.2879654. C.-S. Liao and J.-G. Hwu, “Remote Gate-Controlled Negative Transconductance in Gated MIS Tunnel Diode,” IEEE Transactions on Electron Devices, vol. 63, no. 7, pp. 2864-2870, July 2016. doi: 10.1109/TED.2016.2565688. H.-W. Lu, T.-Y. Chen, and J.-G. Hwu, “Electrical Characteristics Analysis at Oxide Flat-Band Voltage for Al-SiO2-Si Capacitor,” ECS Trans., vol. 35, issue 4, pp. 639-650, 2011. doi: 10.1149/1.3572310. T.-Y. Chen, H.-W. Lu, and J.-G. Hwu, “ Effect of H2O on the electrical characteristics of ultra-thin SiO2 prepared with and without vacuum treatments after anodization,” Microelectronic Engineering, vol. 104, pp. 5-10, April 2013. doi: 10.1016/j.mee.2012.11.005. Y.-K. Lin and J.-G. Hwu, 'Role of Lateral Diffusion Current in Perimeter-Dependent Current of MOS(p) Tunneling Temperature Sensors,' IEEE Transactions on Electron Devices, vol. 61, no. 10, pp. 3562-3565, Oct. 2014. doi: 10.1109/TED.2014.2346238. Y.-K. Lin and J.-G. Hwu, 'Photosensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,' IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3217-3222, Sept. 2014. doi: 10.1109/TED.2014.2334704. S. M. Sze and K. K. Ng, Physics of Semiconductor Devices, 3rd ed., Hoboken, NJ, USA: Wiley, 2007. C.-F. Yang and J.-G. Hwu, 'Tunable Negative Differential Resistance in MISIM Tunnel Diodes Structure With Concentric Circular Electrodes Controlled by Designed Substrate Bias,' IEEE Transactions on Electron Devices, vol. 64, no. 12, pp. 5230-5235, Dec. 2017. doi: 10.1109/TED.2017.2757506. C.-F. Yang and J.-G. Hwu, 'Light-to-Dark Current Ratio Enhancement on MIS Tunnel Diode Ambient Light Sensor by Oxide Local Thinning Mechanism and Near Power-Free Neighboring Gate,' IEEE Transactions on Electron Devices, vol. 65, no. 5, pp. 1810-1816, May 2018. doi: 10.1109/TED.2018.2818187. M. Depas, T. Nigam, and M. M. Heyns, 'Soft Breakdown of Ultra-Thin Gate Oxide Layers,' IEEE Transactions on Electron Devices, vol. 43, no. 9, pp. 1499-1504, Sept. 1996. doi: 10.1109/16.535341. J. Sune, E. Miranda, M. Nafria, and X. Aymerich, 'Point contact conduction at the oxide breakdown of MOS devices,' International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217), San Francisco, CA, USA, 1998, pp. 191-194. doi: 10.1109/IEDM.1998.746318. E. Miranda, J. Sune, R. Rodriguez, M. Nafria, X. Aymerich, L. Fonseca, and F. Campabadal, 'Soft breakdown conduction in ultrathin (3-5 nm) gate dielectrics,' IEEE Transactions on Electron Devices, vol. 47, no. 1, pp. 82-89, Jan. 2000. doi: 10.1109/16.817571. P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” Journal of the Electrochemical Society, vol. 104, pp. 230–236, 1957. doi: 10.1149/1.2428542. M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation,” Journal of Molecular Structure, vol. 480-481, pp. 607-610, 1999. doi: 10.1016/S0022-2860(99)00017-4. (2015). SILVACO Atlas User’s Manual of Version 5.21.2.R. Accessed: Jul. 1. 2019. [Online]. Available: http://www.silvaco.com J.-Y. Cheng and J.-G. Hwu, 'Characterization of Edge Fringing Effect on the C-V Responses From Depletion to Deep Depletion of MOS(p) Capacitors With Ultrathin Oxide and High-k Dielectric,' IEEE Transactions on Electron Devices, vol. 59, no. 3, pp. 565-572, March 2012. doi: 10.1109/TED.2011.2178605. Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, Y. Yamaguchi, T. Mizutani, M. Kobayashi, and T. Hiramoto, 'Novel single p+poly-Si/Hf/SiON gate stack technology on silicon-on-thin-buried-oxide (SOTB) for ultra-low leakage applications,' Symposium on VLSI Technology (VLSI Technology), Kyoto, pp. T170-T171., 2015. doi: 10.1109/VLSIT.2015.7223665. T. Hiramoto, K. Takeuchi, T. Mizutani, A. Ueda, T. Saraya, and M. Kobayashi, Y. Yamamoto, H. Makiyama, T. Yamashita, H. Oda, S. Kamohara, N. Sugii, and Y. Yamaguchi, 'Ultra-low power and ultra-low voltage devices and circuits for IoT applications,' IEEE Silicon Nanoelectronics Workshop (SNW), Honolulu, HI, pp. 146-147, 2016. doi: 10.1109/SNW.2016.7578025. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/62194 | - |
dc.description.abstract | 本篇論文旨在以製程技術和理論計算模擬的方式,探討氧化層局部薄化對電荷耦合金氧半(P型)穿隧二極體特性的影響。不同於過往以破壞性的方法對氧化層施加一段時間正偏壓達到等效局部薄化的效果,本篇提出在閘/汲極氧化層製作局部薄化的結構,發現其仍能使此種元件擁有良好電晶體特性。
在第二章中,我們首先呈現在閘/汲極的局部薄化氧化層分別對元件轉移特性的影響,可以看到若閘極氧化層存在此結構,能使該元件展現出低於60 mV/decade的次臨界擺幅,而若汲極氧化層存在此結構,則整體工作電壓能再大幅降低。此外,透過改變局部薄化氧化層區域的數量和面積,元件的次臨界擺幅得以進一步降至8.4 mV/decade,並維持三個級距的電流大小。 在第三章中,我們呈現局部薄化氧化層厚度對元件臨界電壓值和漏電流大小的強烈影響。具體而言,愈薄的氧化層厚度能使元件臨界電壓值愈往平能帶電壓靠近,然而由於漏電流也因此增大,使最後得到的次臨界擺幅未必更低,甚至可能變高。因此,對於局部薄化氧化層厚度的控制,在該元件低功耗操作考量之下,是個非常重要的環節。 最後,在本篇論文各個章節的討論中,亦利用二維TCAD模擬計算輔助,闡述關於局部薄化氧化層結構其物理參數對此種元件的影響,例如數量、面積以及厚度,並以實驗數據作為佐證。我們根據實驗和模擬結果,可以對氧化層局部薄化效應做出更完整的描述與結論,期望使電荷耦合金氧半穿隧二極體能成為未來低功耗應用的潛在方案之一。 | zh_TW |
dc.description.abstract | In this thesis, oxide local thinning (OLT) effects on the performance of charge-coupled metal-insulator semiconductor tunnel diodes (MIS TDs) with p-type substrate were characterized through process techniques and simulation. Unlike the destructive and uncontrollable treatment of positive voltage stress (PVS) method applied to the oxide layer as reported before, such a device with fabricated OLT regions at the gate and drain was found to present desirable characteristics as a transistor with low power consumption.
In Chapter 2, the overview of OLT effects realized by fabrication on the transfer characteristics of the charge-coupled MIS TDs was given. With OLT regions at the gate, sub-60 mV/decade subthreshold swing (SS) of such a device could be obtained at room temperature, whereas the operating voltage could be largely reduced with those at the drain. Also, by adjusting the number and area of the OLT regions, SS could be possibly optimized to a much lower value, e.g., 8.4 mV/decade over 3 current decades. In Chapter 3, threshold voltage (VT) and leakage current of such a device was found strongly affected by the thickness of the OLT regions. Specifically, VT could be tuned closer to the flat-band voltage by thinning the OLT thickness. However, SS was also compromised when the leakage current level was raised with thinner oxide. Therefore, a precise control of this process parameter would be of great importance for low power consideration. TCAD 2-D simulation was carried out to explain the roles of several physical parameters, such as the number, area, and thickness of the OLT regions throughout this thesis. The results corresponded with the observation from the experiments, and the conclusion was made on such devices having the potential for low power applications in the near future. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T13:33:04Z (GMT). No. of bitstreams: 1 ntu-109-R07943058-1.pdf: 3482990 bytes, checksum: a8f5545e5d4adcd63c419743423f75e4 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 摘要………………………………………………………………I
Abstract………………………………………………………II Contents………………………………………………………IV Figure Captions………………………………………………VI Chapter 1 Introduction………………………………………1 1-1 Motivation…………………………………………………………1 1-2 I-V Characteristics of MIS (Al/SiO2/p-Si) Tunnel Diodes…………3 1-3 Electrical Characteristics of Charge-Coupled MIS(p) Tunnel Diodes with Concentric Gate………………………………………………6 1-4 Lateral Transport Efficiency Enhancement of Inversion Carriers……8 1-5 Thesis Organization………………………………………………10 Chapter 2 Charge-Coupled MIS(p) Tunnel Diodes with Engineered Oxide Local Thinning Layers 2-1 Introduction………………………………………………………23 2-2 Experimental………………………………………………………24 2-3 Effects of Oxide Local Thinning :Layers by Process Techniques……………26 2-4 Dependence of Gate Oxide Local Thinning Effects on the Effective Tunneling Area……………………………………………………28 2-5 Low Power Consideration with Oxide Local Thinning Region at Drain………………………………………………………………31 Chapter 3 Effects of Oxide Local Thinning Thickness 3-1 Introduction………………………………………………………45 3-2 Threshold Voltage Tuning by OLT Thickness Control……………..46 3-3 Consideration for Leakage Current Level…………………………...48 Chapter 4 Conclusion and Future Work 4-1 Conclusion…………………………………………………………55 4-2 The Best Case in This Work…………………………………………56 4-3 Characterization of Oxide Local Thinning Effects in 3-D…………57 References……………………………………………………62 Publication List……………………………………………67 | |
dc.language.iso | zh-TW | |
dc.title | 氧化層局部薄化對具同心環閘極控制電荷耦合金氧半穿隧二極體特性影響之探討 | zh_TW |
dc.title | Characterization of Oxide Local Thinning Effects on Charge-Coupled MIS(p) Tunnel Diodes with Concentric Gate | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林浩雄,鄭晃忠 | |
dc.subject.keyword | 電晶體,金氧半穿隧二極體,低功耗, | zh_TW |
dc.subject.keyword | Transistors,MIS tunnel diodes,Low power, | en |
dc.relation.page | 67 | |
dc.identifier.doi | 10.6342/NTU202001026 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-06-17 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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