應用於DisplayPort Version 1.2且具有自動選頻技巧之多速率交流耦合接收器

Abstract

隨著製程的進步，今日的電子產品對於影音檔案的傳輸量與傳輸速度的要求愈來愈高，序列式高速傳輸介面如PCI Express、HDMI和DisplayPort近來被廣泛的使用，因此在這些介面中使用高速的傳送器和接收器成為下一個高清顯示世代的趨勢。 本論文提出一個多速率且具有自動選頻技巧之交流耦合接受器，此接受器可支援DisplayPort Version 1.2規格中的1.62 Gb/s、2.7 Gb/s和5.4 Gb/s並新增一個擴充規格的資料速率8.1 Gb/s。在接受電路方面，此系統實現了一個寬頻的交流耦合連接電路，此電路使用了一個脈衝轉換器將脈衝訊號快速地轉換為不歸零資料。在資料回復方面，此系統使用半速率架構的時脈資料回復電路，所以在迴路中採用半速率的線性相位偵測器和半速率的頻率偵測器，分別用來鎖定相位和頻率。此系統採用一個多頻帶的壓控震盪器以支援規格中的三種資料速率及降低壓控震盪器的增益。由於壓控震盪器需要控制訊號以選擇正確的頻段，此頻段選擇器能夠自動且迅速地偵測資料速率並提供控制訊號給壓控震盪器。 此系統實現於台積電90 nm 1P9M CMOS製程，當輸入資料速率為5.4 Gb/s時，其回復資料抖動為20.2 ps(峰對峰值)及3.15 ps(方均根植);其回復時脈抖動為15.1 ps(峰對峰值)及2.13 ps(方均根植)。1.62 Gb/s、2.7 Gb/s和5.4 Gb/s的位元錯誤率皆通過10-12的測試。當系統操作於1.2伏特的電壓下，不計算輸出緩衝器的功率消耗為90毫瓦。此晶片總面積為1 mm2，電路有效面積為0.23 mm2。

With the advances of fabrication process, today’s electronic devices are capable of greater data capacity and faster data transmission in multimedia systems that require the serialized high speed interfaces such as PCI Express, HDMI and DisplayPort to be widely used these days. In other words, using high speed transmitters and receivers in these interfaces has become the trend of the next generation of high resolution displays. A multi-rate AC-coupled receiver with automatic band selection is designed to support data rates of 1.62 Gb/s, 2.7 Gb/s and 5.4 Gb/s for DisplayPort Version 1.2 and an extra data rate of 8.1 Gb/s for specification extension. A wide bandwidth AC coupled interconnect is realized by using a pulse converter with positive feedback path to rapidly transform pulse signals into NRZ data. Half-rate architecture is adopted in the designed clock and data recovery (CDR) circuit so the half-rate linear phase detector and the half-rate digital quadricorrelator frequency detector are used to lock the phase and frequency respectively. The modified multi-band voltage controlled oscillator (VCO) is designed to provide a low VCO gain (KVCO). Because the VCO requires control signals to select the correct band, the automatic band selector enables the multi-rate operation of the receiver. We fabricated this receiver using TSMC 90nm CMOS technology. When the input data rate is 5.4 Gb/s, the recovered 5.4 Gb/s data shows the peak-to-peak jitter of 20.2 ps and the rms jitter of 3.15 ps. The recovered 2.7 GHz clock shows the peak-to-peak jitter of 15.1 ps and the rms jitter of 2.13 ps. The BER is less than 10-12. The power dissipation without output buffers is 90 mW under a 1.2 V supply. This chip occupies a total area of 1 mm2 and the core area occupies an area of 0.23 mm2.