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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 王暉(Huei Wang) | |
dc.contributor.author | Tzu-Chien Tang | en |
dc.contributor.author | 唐子兼 | zh_TW |
dc.date.accessioned | 2021-06-16T10:36:49Z | - |
dc.date.available | 2024-07-03 | |
dc.date.copyright | 2020-07-27 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-07-23 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60927 | - |
dc.description.abstract | 本論文總共分成兩部分,第一部分是一個38 GHz 升頻器,使用65奈米互補式金屬氧化物半導體製程來設計。第二部分是一個Ka頻段的低相位變化可變增益放大器,也使用65奈米互補式金屬氧化物半導體製程來設計。 在第一部分,提出了一個在本地訊號端使用四倍頻器的38 GHz升頻器,用於5G毫米波發射器系統應用。為了使用5 GHz 本地振盪訊號源將2 GHz中頻信號變頻至38 GHz 射頻訊號,採用了次諧波混頻器和四倍頻器。由於混頻器的高本地振盪功率需求,四倍頻器被設計以疊接組態為輸出級來達到高功率四階諧波輸出。此外,本論文也描述了用於實現高二階諧波輸出功率的倍頻器設計流程。在混頻器和四倍頻器的直流功耗分別為42 mW和120 mW的情況下,此調製器在37.5-38.5 GHz上實現了2.5 dB的轉換增益和-9.5 dBm的輸出1dB功率壓縮點(OP1dB)。此升頻器表現大於47 dBc的本地訊號端到輸出射頻訊號端之隔離度以及高於32 dBc的鏡像抑制率。此外由於高隔離度和高鏡像抑制率的性能,升頻器展示出在38 GHz的操作頻率下量測64-QAM的調變信號達到1.5 Gb/s的資料傳輸速度。 在第二部分,提出了一個Ka頻段的高增益控制範圍以及低相位變異的可變增益放大器。藉由電流重用技術(Current-reused)和中和穩定技術(neutralization)達成在寬帶頻率範圍內實現低相位變化性能,因為它們減少了會增加相位變化的寄生電容。而且,通過採用這些技術,此電路還同時具有高增益控制範圍和節省芯片面積的優點,這與傳統的電流抽取(Current-steering)架構有所不同。此提出的Ka頻段可變增益放大器在在 30.8 到 36.5 GHz 的 3-dB 頻寬範圍內獲得 22 dB 的最大增益,並在30至34 GHz頻率範圍內的11°相位變化下展示了23.7 dB的增益控制範圍。 | zh_TW |
dc.description.abstract | This thesis consists of two parts. The first part is a 38 GHz up-converter in 65-nm CMOS process. The second part is a Ka-band high gain control range and low phase variation variable gain amplifier (VGA) with current-reused technique in 65-nm CMOS process. In the first part, a 38 GHz sub-harmonic up-converter using LO frequency quadrupler in 65-nm CMOS for the 5G millimeter-wave (MMW) transmitter application is presented. To up-convert the 2 GHz IF signal to 38 GHz RF using the 5 GHz LO source, sub-harmonic mixers and frequency quadrupler are adopted. Due to the high LO power requirement of mixers, the power stage of frequency quadrupler is designed as cascode configuration to generate larger high level harmonic output power. In addition, the design flow of the frequency doubler used to achieve high second harmonic output power is demonstrated. The proposed up-converter achieves a conversion gain of 2.5 dB and an OP1dB of -9.5 dBm over 37.5-38.5 GHz with 42-mW and 120-mW dc power dissipation of the mixers and frequency quadrupler, respectively. The up-converter performs -47-dBc 8LO-to-RF isolation and better than -32-dBc IRR. Furthermore, due to the high 8LO-to-RF isolation and IRR performances, the 64 quadratic amplitude modulation (QAM) with 1.5 Gb/s data rate is demonstrated at 38 GHz. In the second part, a Ka-band VGA with high gain control range and low phase variation using 65-nm CMOS process is proposed. The performance of low phase variation over wide bandwidth is achieved by the current-reused and neutralization techniques because they reduce the parasitic capacitance that will increase the phase variation. Moreover, by adopting these techniques, it also has the advantages of high gain control range and saving chip area, which is different from traditional current-steering topologies. The proposed VGA achieves peak gain of 22 dB with 3-dB bandwidth from 30.8 to 36.5 GHz and demonstrates 23.7 dB gain control range with 11° phase variation from 30 to 34 GHz. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T10:36:49Z (GMT). No. of bitstreams: 1 U0001-0107202021220600.pdf: 6220463 bytes, checksum: 872312016b79799d46c3822df355e80e (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 誌謝 i 中文摘要 ii ABSTRACT iii CONTENTS v LIST OF FIGURES viii LIST OF TABLES xv Chapter 1 Introduction 1 1.1 Background and Motivation 1 1.2 Literature Survey 2 1.2.1 Frequency Doubler 2 1.2.2 Up-Converter and I/Q Modulator 3 1.2.3 Variable Gain Amplifier 4 1.3 Contributions 5 1.3.1 38-GHz Sub-Harmonic Up-Converter 6 1.3.2 Ka-Band Variable Gain Amplifier 6 1.4 Thesis Organization 7 Chapter 2 A 38-GHz Sub-Harmonic Up-Converter Using LO Frequency Quadrupler in 65-nm CMOS 8 2.1 Introduction 8 2.2 Circuit Design 10 2.2.1 Sub-Harmonic Mixer 11 2.2.2 Design of Frequency Quadrupler 14 2.2.3 Wilkinson Power Divider and 45° Phase Shifter 26 2.2.4 Overall Simulation Results 29 2.3 Experimental Results and Discussions 32 2.3.1 Experimental Results and Discussions of Frequency Quadrupler 33 2.3.2 Experimental Results and Discussions of Up-converter 42 2.4 Summary 49 Chapter 3 Design of High Gain Control Range and Low Phase Variation Ka-Band Variable Gain Amplifier with Current-Reused Technique in 65-nm CMOS 50 3.1 Design Concepts of High Gain Control Range 51 3.1.1 Comparison of Gain Control Range of Three Current-steering Topologies 51 3.1.2 Improvement of Gain Control Range with Neutralization Technique 55 3.2 Design Concepts of Low Phase Variation 56 3.2.1 Phase Analysis of Conventional Current-steering Topology [43] 57 3.2.2 Phase Analysis of Current-steering Topology with Current-reused Technique 60 3.3 Circuit Implementation 64 3.3.1 Circuit Architecture 64 3.3.2 Design of Differential Common Source Amplifier 66 3.3.3 Device Selection for Current-Steering Topology 70 3.3.4 Circuit Schematic and Simulation Results 71 3.4 Experimental Results and Discussions 78 3.5 Summary 89 Chapter 4 Conclusion 90 REFERENCE 92 | |
dc.language.iso | en | |
dc.title | 應用於5G無線系統之毫米波升頻器及可變增益放大器之設計 | zh_TW |
dc.title | Design of Millimeter-Wave Up-Converter and VGA for 5G Application | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 黃天偉(Tian-Wei Huang),林坤佑(Kun-You Lin),張鴻埜(Hong-Yeh Chang),蔡作敏(Zuo-Min Tsai) | |
dc.subject.keyword | 互補式金屬氧化物半導體,升頻器,毫米波,鏡像抑制率,Ka頻段,可變增益放大器, | zh_TW |
dc.subject.keyword | CMOS,up-converter,millimeter-wave,image reject ratio,variable gain amplifier,Ka-band, | en |
dc.relation.page | 97 | |
dc.identifier.doi | 10.6342/NTU202001253 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-07-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
顯示於系所單位: | 電信工程學研究所 |
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