請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60865
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 林浩雄 | |
dc.contributor.author | Zhe-Wei Yang | en |
dc.contributor.author | 楊哲維 | zh_TW |
dc.date.accessioned | 2021-06-16T10:33:46Z | - |
dc.date.available | 2018-08-26 | |
dc.date.copyright | 2013-08-26 | |
dc.date.issued | 2013 | |
dc.date.submitted | 2013-08-14 | |
dc.identifier.citation | 參考文獻
[1] K. Mistry, “Intel’s Revolutionary 22 nm Transistor Technology”, p.10,2011, http://download.intel.com/newsroom/kits/22nm/pdfs/ 22nm-Details_Presentation.pdf [2] M. Sze, “Physics of semiconductor devices”, 3rd Ed, Wiley, p.328, 2007. [3] D. J. Frank, R. H. Dennard, et al., “Device scaling limits of Si MOSFETs and their application dependencies”, Proc. IEEE, Vol.89, p. 259, 2001. [4] G. Wilk, R. Wallace, et al., “High-K gate dielectric: Current status and materials properties considerations”, J. Appl. Phys., Vol. 89, p.5243, 2001. [5] E. Yu, D. Wang, et al., “High electron mobility InAs nanowire field-effect transistors”, Small, Vol. 3, p. 326, 2007. [6] A. Kranti, G. Armstrong, “Performance assessment of nanoscale double- and triple-gate FinFETs”, Semicond. Sci. Technol., Vol. 21, p. 409, 2006. [7] L. Samuelson, L. Wallenberg, et al., “Size, shape, and position-controlled GaAs nano-whiskers”, Appl. Phys. Lett., Vol. 79, p. 3335, 2001. [8] M. Koguchi, H. Kakibayashi, et al., “Growth and optical properties of nanometer-scale GaAs and InAs whiskers”, J. Appl. Phys., Vol. 77, p. 447, 1995. [9] T. Bryllert, L. Wernersson, et al., “Vertical high mobility wrap-gated InAs nanowire transistor”, IEEE Electron Device Lett., Vol. 27, p. 323, 2006. [10] B. Yu, L. Chang, et al., “FinFET scaling to 10nm gate length”, IEEE Electron Device Meeting, p. 251, 2002. [11] S. Dhara, S. Sengupta, et al., “Facile fabrication of lateral nanowire wrap-gate devices with improved”, Appl. Phys. Lett., Vol. 99, p. 173101, 2011. [12] M. Panish, “Molecular Beam Epitaxy of GaAs and InP with Gas Source for As and P”, J. Electrochem. Soc.: Solid state science and technology, Vol. 127, p. 2729, 1980. [13] K. Tomioka, J. Motohisa, et al., “Control of InAs nanowire growth directions on Si”, Nano Lett., Vol. 8, p. 3475, 2008. [14] L. H. Chen, “Structural and optical properties of InAs nanowire ”, master thesis, National Taiwan University, p. 32, 2012. [15] Y. Hoshino, Y. Saito, et al.,“Interdiffusion analysis of Au/Ti and Au/Pt/Ti electrode structures grown on diamond (001) surface by rutherford backscattering spectroscopy”, Jpn. J. Appl. Phys., Vol. 49, p. 101302, 2010. [16] D. Suyatin, C. Thelander, et al., “Sulfur passivation for ohmic contact formation to InAs nanowires”, Nanotechnology, Vol. 18, p. 105307, 2007. [17] S. Dayeh, C. Soci, et al., “Influence of surface states on the extraction of transport parameters from InAs nanowire field effect transistors”, Appl. Phys. Lett., Vol. 90, p. 162112, 2007. [18] M. Leskela, M. Ritala, et al., “Atomic layer deposition chemistry: recent developments and future challenges”, Angew. Chem. Int. Ed.,Vol. 42, p. 5548, 2003. [19] Vogler, Paula, “Where's the metal? ”, Sol. State Technol., Vol.35, p35, 2003. [20] 柯志忠, “以原子層沉積製程成長氧化物薄膜與金屬奈米顆粒 及其應用”, 國研科技, 24期, p. 29, 2009. [21] H. Liu, Q. Kuang, et al., “Frequency dispersion effect and parameters extraction method for novel HfO2 as gate dielectric”, Sci . China, Vol. 53, p. 878, 2010. [22] M. Sze, “Physics of semiconductor devices”, 3rd Ed, Wiley, p. 216, 2007. [23] P. Masson, J.L. Autran, et al., “Frequency characterization and modeling of interface traps in HfSixOy/HfO2 gate dielectric stack from a capacitance point of view”, Appl. Phys. Lett., Vol. 81, p. 3392, 2002. [24] H. Liu, Q. Kuang, et al., “Frequency dispersion reduction and bond conversion on n-GaAs by in-situ surface oxide removal”, Appl. Phys. Lett., Vol. 91, p. 163512, 2007. [25] K. Blekker, A. Matiss, et al., “High-frequency measurements on InAs nanowire field effect transistors using coplanar waveguide contacts”, IEEE Trans. Nanotechnol., Vol. 9, p. 432, 2010. [26] M. Sze, “Physics of semiconductor devices”, 3rd Ed, Wiley, p. 305, 2007. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60865 | - |
dc.description.abstract | 本論文已經成功地完成砷化銦(InAs)奈米線金氧半場效電晶體。奈米線係以分子束磊晶(MBE)法直接由矽(001)指向圖案基板沿[111]方向成長。我們利用電子束微影系統在絕緣基板之上先定義出源極、閘極、汲極,再使用電子束蒸鍍機鍍上金屬,並浮蝕(lift-off)電極圖案。接著再使用電子束微影系統進行二次對準,定義出閘極要沉積氧化層的區域。並以原子層沉積系統沉積高介電係數氧化層氧化鉿(HfO2)。然後再用雙束型聚焦離子束顯微系統(DB-FIB)所附屬的擷取系統(Pick-up system)將砷化銦奈米線安置到源極與汲極金屬電極之間以形成MOS的結構。為了改善奈米線與金屬電極間的接觸電阻,我們利用雙束型聚焦離子束顯微系統沉積鉑(Pt)以“焊接”奈米線與金屬電極,並用快速退火爐退火以獲致源極與汲極的歐姆接觸。目前我們已成功完成,通道寬度~100 nm、閘極長度為~500 nm、轉導值(gm)為2.3 mS/mm以及電子移動率為1630〖 cm〗^2/V-s之砷化銦奈米線電晶體。 | zh_TW |
dc.description.abstract | In this thesis, we have successfully made the InAs nanowire MOSFET. The nanowire was grown in Si/SiO2 nanotrench structure by gas source molecular beam epitaxy (GSMBE). We defined the source, gate, and drain by e-beam lithography. Then we deposited metal by e-beam evaporator, and made the electrodes by lift-off. We defined the region where we wanted to deposit gate oxide by using multiple lithographic steps, and placed the nanowire into the area we wanted by using pick-up system. For improving the ohmic contact between the nanowire and the electrodes by depositing Pt by dual-beam focused ion beam (DB-FIB) then did rapid thermal annealing (RTA). In conclusion, we have succeeded in fabricating the InAs nanowire MOSFET, which gate width is about 100nm, gate length is about 500nm, transconductance is about 2.3 mS/mm, and electron mobility is 1630〖 cm〗^2/V-s. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T10:33:46Z (GMT). No. of bitstreams: 1 ntu-102-R00943111-1.pdf: 2770451 bytes, checksum: 98f5bc6a6679610dcac9e4164b82c290 (MD5) Previous issue date: 2013 | en |
dc.description.tableofcontents | 目錄
第一章 序論 1 1.1 電晶體之發展趨勢 1 1.2 砷化銦材料以及奈米線介紹 2 第二章 砷化銦奈米線金氧半場效電晶體元件製作 8 2.1 砷化銦奈米線成長 8 2.2 砷化銦奈米線歐姆接觸 10 2.3 砷化銦奈米線金氧半場效電晶體製程步驟 14 2.3.1 基板與元件之間絕緣層製作 14 2.3.2 電子束微影技術定義源極、汲極和閘極以及沉積金屬 14 2.3.3 氧化層沉積 17 2.3.4砷化銦奈米線定位以及增加歐姆接觸之焊接 21 第三章 氧化層二氧化鉿製作與分析 24 3.1 MOS電容樣品製作 24 3.2 MOS電容C-V量測結果 25 3.3氧化層二氧化鉿(HfO2)模型建構與推導 29 3.4氧化層二氧化鉿量測與擬合結果 31 第四章 砷化銦奈米線場效電晶體實驗量測結果與分 35 4.1砷化銦奈米線電晶體直流電性量測 35 第五章 結論 40 參考文獻 41 圖目錄 圖1.1.1近年來金氧半場效電晶體結構演進圖 2 圖1.2.1垂直式砷化銦奈米線陣列之SEM影像 5 圖1.2.2垂直式砷化銦奈米線電晶體SEM影像 6 圖1.2.3垂直式砷化銦奈米線電晶體結構示意圖 6 圖1.2.4矽鰭式場效電晶體之SEM影像 7 圖1.2.5水平式砷化銦奈米線場效電晶體之SEM影像 7 圖2.1.1砷化銦奈米線SEM影像,5000倍 9 圖2.1.2砷化銦奈米線SEM影像,20000倍 10 圖2.2.1奈米線歐姆接觸量測結構示意圖 12 圖2.2.2砷化銦奈米線歐姆接觸實驗I-V曲線量測結果 12 圖2.2.3利用FIB沉積Pt於奈米線上之SEM影像 13 圖2.3.1二氧化矽成長於砷化鎵基板結構示意圖 14 圖2.3.2源極、閘極、汲極電極製作完成結構示意圖 16 圖2.3.3製作出源極、汲極、閘極之電SEM影像 16 圖2.3.4定義出二氧化鉿沉積沉積區域光學顯微鏡影像 18 圖2.3.5在閘極沉積出氧化鉿之結構示意圖 20 圖2.3.6電子阻劑因為高溫而失真之光學顯微鏡影像 20 圖2.3.7成功將奈米線放置於特定區域SEM影像 22 圖2.3.8二氧化鉿沉積之區域SEM影像 22 圖3.3.9砷化銦奈米線電晶體SEM影像以及結構示意圖 23 圖3.1.1 MOS電容結構示意圖 24 圖3.2.1 200oC成長之樣品變頻C-V圖形 27 圖3.2.2 250oC成長之樣品變頻C-V圖形 27 圖3.2.3 280oC成長之樣品變頻C-V圖形 28 圖3.2.4 1 kHz下,不同成長之樣品變頻,正掃與負掃C-V圖形 28 圖3.3.1 C-V量測模型 30 圖3.4.1 200oC成長之樣品,不同頻率電容值量測與擬合結果 32 圖3.4.2 200oC成長之樣品,不同頻率電導值量測與擬合結果 32 圖3.4.3 250oC成長之樣品,不同頻率電容值量測與擬合結果 33 圖3.4.4 250oC成長之樣品,不同頻率電導值量測與擬合結果 33 圖3.4.5 280oC成長之樣品,不同頻率電容值量測與擬合結果 34 圖3.4.6 280oC成長之樣品,不同頻率電導值量測與擬合結果 34 圖4.1.1不同VGS下,VDS-IDS電晶體轉換特性曲線圖 38 圖4.1.2 VDS =1.5V時,VGS-IDS電晶體轉換特性曲線圖 38 圖4.1.3從圖4.1.2縱軸開根號,求得VTH= -1.7 (V) 39 表目錄 表1.2.1 Si、Ge、 GaAs、 InAs 室溫下之載子移動率 5 表4.3.1 不同成長溫度之樣品,Co、CT、RT擬合結果 31 | |
dc.language.iso | zh-TW | |
dc.title | 砷化銦奈米線金氧半場效電晶體之製作與特性研究 | zh_TW |
dc.title | Fabrication and Characterization of InAs nanowire
Metal-Oxide-Semiconductor Field-Effect Transistor | en |
dc.type | Thesis | |
dc.date.schoolyear | 101-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 胡振國,毛明華,柯誌欣 | |
dc.subject.keyword | 砷化銦奈米線,金氧半場效電晶體, | zh_TW |
dc.subject.keyword | InAs nanowire,MOSFET, | en |
dc.relation.page | 44 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2013-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-102-1.pdf 目前未授權公開取用 | 2.71 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。