使用65-nm CMOS製程製作之60-Gb/s有線傳輸器

Abstract

在本論文中，實現了一種使用65-nm CMOS製程製作之60-Gb/s傳輸器，其中主要電路包括偽隨機二進制序列產生器、鎖相迴路以及多工器。 在本晶片中的偽隨機二進制序列產生器會輸出四路等相位的15-Gb/s的偽隨機二進制序列，因此在進行量測晶片時不再需要額外的偽隨機二進制序列產生器。 接著是一個30-Gb/s的鎖相迴路，其中包含了一個差動電壓控制震盪器、除數為64的除頻器鏈、一個相位頻率偵測器以及一個三階的迴圈濾波器，其中相位頻率偵測器藉由單邊混頻器與低通濾波器的架構達到壓制參考饋入的目的。 傳輸器的最後一個部分是多工器。四對一的多工器是由兩個30-Gb/s二對一多工器與一個60-Gb/s二對一多工器所組成，其中60-Gb/s二對一多工器包含了60-Gb/s選擇電路和30-Gb/s的重新取樣器，60-Gb/s選擇電路採用基於分佈式放大器的架構，以達到60-Gb/s的操作頻率。 此電路共佔了2.1 × 1 mm2，並在1.5-V的電壓供應下消耗了900 mW的功耗。

In this thesis, a 60-Gb/s transmitter has been implemented in 65-nm CMOS technology, which consists of a 4 x 15-Gb/s 27-1 pseudo random binary sequence (PRBS) generator, a 30-GHz phase-lock-loop (PLL), and a 4-to-1 multiplexer (MUX). The 4 x 15-Gb/s 27-1 PRBS generator can provide four parallel 15-Gb/s data for multiplexers, so no pattern generator is needed when testing the chip. The following is a 30-GHz PLL, consists of a differential voltage-controlled oscillator (VCO), a divider chain with total modulus of 64, a phase and frequency detector, and a third-order loop filter. The phase and frequency detector is based on SSB mixers and with low-pass filters to suppress the reference feedthrough . The last part of the transmitter is a 4-to-1 MUX. This 4-to-1 MUX is extension of 2-to-1 MUX by using two 30-Gb/s 2-to-1 MUXs and a 60-Gb/s 2-to-1 MUX. The 60-Gb/s 2-to-1 MUX consists of a 60-Gb/s 2:1 select circuit and 30-Gb/s input retimers. To enable to operating at 60-Gb/s, the 60-Gb/s 2:1 select circuit is based on distributed amplifiers (DA) to produce the 60-Gb/s data signal. This circuit occupies 2.1 × 1 mm2, and consumes 900 mW from a 1.5-V supply.