高效能背板互連系統之眼圖預測與等化器設計

Abstract

高速背板互連系統中，因互連線的非理想效應而造成的符際干擾，會引發嚴重的信號完整性問題。本論文提出新穎的等化技術和最佳化方法，以補償通道的非理想效應，使其接近理想而消除符際干擾。 首先，根據系統步階響應而開發的快速眼圖預測演算法，可以快速評估高速數位電路的接收端信號品質，正確計算最差情況下的邏輯1和邏輯0電壓值，進而推導出相對應的解析解。接著，介紹如何從步階響應推得組成最差情況眼圖的相對應位元組合，以及利用數個範例來驗證此方法的準確性。 其次，在通訊晶片中會採用有限脈衝響應濾波器作為發射器預加重電路，保持接收端信號有良好的信號完整度，為了得到最佳的係數設計及最佳的眼圖優化，本論文提出新穎的直接眼圖最佳化演算法，設定眼圖遮罩為最佳化的目標函數，為了能更為快速且有效尋找出最佳的參數設定，引入上述的快速眼圖預測演算法，加速眼圖計算模擬的程序，結果顯示此方法將會比起傳統採方式快上數十倍，實驗結果也驗證了此最佳化方法的效果。 接著，提出一種被動式有限脈衝濾波器設計，利用額外插入的殘段所產生的反射信號實現2階的被動式有限脈衝濾波器電路。推導出擬合成的係數和相關的設計參數 (RT, RS, Zh) 之間的關係式，從而建立一通用的設計圖表，使得容易實現此被動式有限脈衝濾波器設計，另外此被動解決方案具有減少功耗並達到有效改善眼圖的好處。 最後在高效能背板互連系統設計上，本論文提出接地面鏤空結構和膠囊型清潔環信號的信號完整度佈線設計，以及一新穎的連續時間線性等化器設計，當資料傳輸率從現在使用的 3 Gb/s 提升到 12 Gb/s，在長 117.5 公分 SATA-II I/O 序列連線的應用上，模擬與測量結果顯示在眼高和時間抖動上，展現了顯著的改善，恢復已被關閉的眼圖。

This dissertation focuses on the developments of fast eye-diagram analyses and equalization techniques for solving the signal-integrity problems caused by the inter-symbol interference (ISI) in the high-performance backplane interconnect system. In the beginning, a worst-case eye-diagram analysis which relates to the step response of the transmission-line system is presented to quickly and accurately evaluate the electrical performance for the general interconnect systems. With the help of the prediction approach, the bounded voltage margins for the worst-case logic 1-state and 0-state are derived analytically. In addition to introducing how to obtain the worst-case bit patterns form the given step response, several examples are shown to demonstrate the accuracy of the developed approach. Secondly based on the finite-impulse response (FIR) filter as the transmitter pre-emphasis, a new design algorithm to directly optimize the eye diagram is proposed to counteract ISI in the high-speed data transmission. It is found that not only the frequency-dependent loss but also the multiple reflections due to impedance mismatch contribute much to ISI. Therefore, a systematic method is proposed to efficiently design FIR filters for the best eye-diagram improvement. The optimal sets of tap coefficients and numbers are thus determined by the direct eye-diagram optimization according to the target eye-masks as the objective function. Subsequently, the equalization results for counteracting the multiple reflections and lossy material problems are given to demonstrate the remarkable mitigation of ISI effects. Experimental results are also presented to validate the efficiency of the proposed method for the elimination of the ISI problems due to the multiple reflections and frequency-dependent loss. Furthermore, a passive FIR filter design is proposed to realize the de-emphasis function by taking the advantage of reflections under the additional inserting stub. The relations between the synthesized tap coefficients and the corresponding design parameters (RT, RS, Zh) are derived analytically and thus a universal design chart is well established to facilitate the passive FIR filter design. The passive solution has the advantages of reducing the power consumption of the transmitters and achieving the eye-diagram improvement efficiently. Finally, the systematic integration of signal-integrity aware layouts and the new continuous-time linear equalizer (CTLE) are proposed for enhancing the high-performance backplane interconnects system. First, the SI-aware layouts of patterned ground structure and capsule-shaped anti-pad are presented to enhance the connector performance. In addition, a new differential CTLE by taking the advantage of differential via-stubs is proposed to restore the eye-diagram deterioration in serial I/O links. Their application for a 117.5-cm SATA-II link demonstrates the significant improvement in the eye height and timing jitter. Furthermore, a viable approach is suggested to successfully re-open the eyes while the data rate increases from the current 3 Gb/s to 12 Gb/s. The measurement results are also provided to validate the proposed design concepts.