請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60229完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳耀銘(Yaow-Ming Chen) | |
| dc.contributor.author | Hung-Jyun Chen | en |
| dc.contributor.author | 陳竑鈞 | zh_TW |
| dc.date.accessioned | 2021-06-16T10:13:57Z | - |
| dc.date.available | 2018-08-26 | |
| dc.date.copyright | 2013-08-26 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-08-19 | |
| dc.identifier.citation | [1]G. Moschopoulos and P. Jain, 'Single phase single stage power factor -corrected-converter topologies,' IEEE Trans. on Industrial Electronics, vol. 52, no. 1, pp. 23-35, 2005..
[2]R. Martinez and P. N. Enjeti, “A high-performance single-phase rectifier with input power factor correction, ” IEEE Trans. on Power Electronics, vol. 11, no. 2, pp. 311-317, 1996. [3]M. M. Jovanovic and Yungtaek Jang, 'State-of-the-art, single-phase, active power-factor-correction techniques for high-power applications an overview,' IEEE Trans. on Industrial Electronics, , vol.52, no.3, pp.701,708, 2005 [4]A. R. Prasad, P. D. Ziogas, and S. Manias, 'A new active power factor correction method for single-phase buck-boost AC-DC converter,' APEC, pp.814,820, 1992. [5]J. -J. Lee, J. -M. Kwon, E. -H. Kim, W. -Y. Choi, and B.-H. Kwon, 'Single-Stage Single-Switch PFC Flyback Converter Using a Synchronous Rectifier,' IEEE Trans. on Industrial Electronics,vol.55, no.3, pp.1352,1365, 2008. [6]Jingquan Chen, D. Maksimovic, and R.W. Erickson 'Analysis and design of a low-stress buck-boost converter in universal-input PFC applications,' IEEE Trans. on Power Electronics , vol.21, no.2, pp.320,329, 2006. [7]L. Huber, G. Liu, and M.M. Jovanovic, 'Design-Oriented Analysis and Performance Evaluation of Buck PFC Front End,' IEEE Trans. on Power Electronics , vol.25, no.1, pp.85,94, 2010. [9]L. Huber, Yungtaek Jang, and M. M. Jovanovic, 'Performance Evaluation of Bridgeless PFC Boost Rectifiers,' IEEE Trans. on Power Electronics, , vol.23, no.3, pp.1381,1390, 2008. [10]R. Watson, and F. C. Lee, 'A soft-switched, full-bridge boost converter employing an active-clamp circuit,' PESC, vol.2, pp.1948,1954 vol.2, 1996. [11]R. Srinivasan, and R. Oruganti, 'A unity power factor converter using half-bridge boost topology,' IEEE Trans. on Power Electronics, vol.13, no.3, pp.487,500, 1998 [12]J. -S. Lai, and D. Chen, “Design consideration for power factor correction boost converter operating at the boundary of continuous conduction mode and discontinuous conduction mode,” APEC , pp.267-273,1993 [13]X. Xu, W. Liu, and A. Q. Huang, 'Two-Phase Interleaved Critical Mode PFC Boost Converter With Closed Loop Interleaving Strategy,' IEEE Trans. on Power Electronics, vol.24, no.12, pp.3003,3013, 2009 [14]L. Huber, B. T. Irving, and M. M. Jovanovic, 'Closed-Loop Control Methods for Interleaved DCM/CCM Boundary Boost PFC Converters,' APEC, pp.991,997, 2009. [15]K. -M. Ho, C. -A Yeh, and Y. -S. Lai, 'Novel Digital-Controlled Transition Current-Mode Control and Duty Compensation Techniques for Interleaved Power Factor Corrector,' IEEE Trans. on Power Electronics, , vol.25, no.12, pp.3085,3094, 2010 [16]Hangseok Choi, 'Novel adaptive master-slave method for interleaved boundary conduction mode (BCM) PFC converters,' APEC , pp.36,41, 21-25 ,2010. [17]J. -R. Tsai, T. -F. Wu, C.-Y. Wu, Y. -M. Chen, and Ming-Chuan Lee, 'Interleaving Phase Shifters for Critical-Mode Boost PFC,' IEEE Trans. on Power Electronics, vol.23, no.3, pp.1348,1357, 2008 [18]L. Huber, B.T. Irving, and M.M. Jovanovic, 'Open-Loop Control Methods for Interleaved DCM/CCM Boundary Boost PFC Converters,' IEEE Trans. on Power Electronics, vol.23, no.4, pp.1649, 1657, July 2008. [19]L. Huber, B.T. Irving, C. Adragna, and M.M. Jovanovic, 'Implementation of open-loop control for interleaved DCM/CCM boundary boost PFC converters,' APEC, pp.1010,1016, 2008. [20]Bing Lu, 'A novel control method for interleaved transition mode PFC,' APEC, pp.697,701, 2008. [21]C. -P. Ku, D. Chen, C. -S. Huang, and C. -Y. Liu, 'A Novel SFVM-'M' ^3 Control Scheme for Interleaved CCM/DCM Boundary-Mode Boost Converter in PFC Applications,' IEEE Trans. on Power Electronics, , vol.26, no.8, pp.2295,2303, 2011. [22]Jindong Zhang, M. M. Jovanovic, and F. C. Lee, 'Comparison between CCM single-stage and two-stage boost PFC converters,' APEC, pp.335,341 vol.1, 1999. [23]K. Taniguchi and Y. Nakaya, 'Analysis and improvement of input current waveforms for discontinuous-mode boost converter with unity power factor,' Power Conversion Conference, vol.1, pp.399,404 vol.1, 1997. [24]Kai Yao, Xinbo Ruan, Xiaojing Mao, and Zhihng Ye, 'DCM boost PFC converter with high input PF,' APEC, pp.1405, 1412, 21-25, 2010. [25]J. W. Kim, S. M. Choi, K. T. Kim, 'Variable On-time Control of the Critical Conduction Mode Boost Power Factor Correction Converter to Improve Zero-crossing Distortion,' International Conference on PEDS,vol.2, pp.1542,1546, 2005. [26]Mike O’Loughin, “An Interleaved PFC Pre-regulator for High-Power Converters,” Texas Instruments Power Supply Design Seminer, SME1700, 2006. [27]劉智遠，「多相交錯臨界模式功率因數修正電路之電容電流漣波及相電流不穩定效應分析」，國立台灣大學電機工程研究所碩士論文，民國98年。 [28]dsPIC30F1010/202X Data Sheet,Microchip,2006. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60229 | - |
| dc.description.abstract | 臨界模式升壓型轉換器作為功因校正電路，具有高功率因數與柔性切換的效果。在中高功率的應用電路上，為了減少輸入端之電流漣波成分，通常會採用多相交錯控制策略。在各式不同交錯控制策略中，同步導通電壓模式(Synchronized turn-on voltage mode)的控制方式簡易，且其各組電路之相位差皆能維持在一固定量。但電路在操作過程中若遇到擾動，則可能使電感電流無法維持在臨界導通模式而無法達成柔性切換。
本論文針對同步導通訊號電壓控制模式的擾動問題提出一種新型而簡單有效的補償方式，並以實作驗證其正確性。論文中先介紹各種單相升壓型功因校正轉換器的操作模式，並整理各種操作模式之優缺點。接著介紹多相交錯的控制策略及擾動造成的影響，然後詳細說明本論文所提出新型補償方式。最後以微控制器(Micro-Controller Unit, MCU)為控制核心，實作一組600W，多相交錯控制之臨界導通升壓型功因校正電路，以驗證此補償方式之正確性。 | zh_TW |
| dc.description.abstract | Boost type power factor correction (PFC) converter operated in critical conduction mode (CRM) can achieve high power factor and soft switching features. In medium-to-high power level applications, multi-channel interleaved control method was commonly adopted to reduce input ripple current. Among various kinds of interleaved control methods, synchronized turn on voltage mode is easier to implement and each sub-circuit can operate with a fixed phase shift. However, if a perturbation happened to the control signal, the inductor current will fail to maintain critical conduction mode and is not able to achieve the soft feature.
This thesis proposes a simple and effective compensation method to solve the perturbation problem for synchronized turn on voltage mode, and verifies its validity by hardware implementation. In this thesis, different types of operation principles as well as their advantages and disadvantages for the boost PFC converter will be introduced. The multi-channel interleaved control methods for CRM operation and the impact of the control signal perturbation will be presented. Then, the proposed method to compensate the control signal perturbation problem for the multi-channel interleaved PFC converter will be explained in detail. Finally, experimental results obtained from a 600W prototype circuit with micro-controller unit are presented to verify the validity of the proposed compensation method. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T10:13:57Z (GMT). No. of bitstreams: 1 ntu-102-R00921070-1.pdf: 3700066 bytes, checksum: 9d392648b1ec57714779dae64168cb70 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 口試委員會審定書 #
誌謝 i 摘要 ii ABSTRACT iii 目錄 iv 圖目錄 vii 表目錄 xiii 第一章 緒論 1 1.1 研究背景及動機 1 1.2 文獻回顧 3 1.3 章節概要 5 第二章 功率因數校正電路之操作原理及特性 6 2.1 功率因數及總諧波失真的定義 6 2.2 升壓型功率因數校正器之原理 7 2.3 升壓型功因校正電路之操作模式 9 2.3.1 連續導通模式之功率因數校正 10 2.3.2 不連續導通模式功因校正電路 14 2.3.3 臨界導通模式功因校正電路 16 2.3.4 各導通模式之討論 19 2.4 總結 22 第三章 多相交錯式升壓型臨界導通功因校正電路 23 3.1 多相交錯式臨界導通功因校正電路 23 3.2 三相交錯之電路動作時序分析 26 3.2.1 責任週期D < 0.33之動作模式 26 3.2.2 責任週期0.33 < D < 0.67之動作模式 29 3.2.3 責任週期0.67 < D < 1之動作模式 32 3.2.4 責任週期與輸入電流漣波之關係 35 3.3 臨界導通模式之開迴路交錯控制策略 37 3.3.1 同步導通訊號[18] 38 3.3.2 同步截止訊號[18] 44 3.3.3 交錯控制特性之比較 48 第四章 步階式導通時間補償策略 52 4.1 前言 52 4.2 電路架構及操作原理 53 4.2.1 相位延遲電路 54 4.2.2 操作模式偵測裝置 56 4.2.3 導通時間調整電路 58 第五章 交錯式升壓型功因校正電路之設計 61 5.1 電器規格 61 5.2 功率級元件參數設計 62 5.2.1 儲能電感設計 62 5.2.2 功率元件選擇 63 5.2.3 輸出電容選擇 64 5.3 控制級週邊電路設計 64 5.3.1 零電流偵測電路 64 5.3.2 電壓回授電路 66 5.3.3 突波電流抑制之電路設計 67 5.4 系統軟體規劃 68 5.4.1 微控制器簡介 68 5.4.2 軟啟動(Soft Start)之程式規劃流程 68 5.4.3 單組功因校正電路之主程式規劃流程 70 5.4.4 交錯控制及導通時間補償之程式規劃流程 71 第六章 模擬波形與實驗結果 74 6.1 步階式導通時間補償方式之波形模擬 74 6.2 硬體電路之實驗波形驗證 80 6.2.1 步階式導通時間補償方式之實驗波形驗證 80 6.2.2 硬體實測之波形 87 第七章 結論與未來發展 96 7.1 結論 96 7.2 未來發展 96 參考文獻 97 | |
| dc.language.iso | zh-TW | |
| dc.subject | 交錯控制 | zh_TW |
| dc.subject | 升壓型轉換器 | zh_TW |
| dc.subject | 功因校正 | zh_TW |
| dc.subject | 臨界導通 | zh_TW |
| dc.subject | power factor correction | en |
| dc.subject | boost converter | en |
| dc.subject | interleaved control | en |
| dc.subject | critical conduction | en |
| dc.title | 交錯式臨界導通升壓型功因校正電路之研製 | zh_TW |
| dc.title | Design and Implementation of an Interleaved CRM Boost PFC Converter | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 101-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳德玉(Dan Chen),賴炎生(Yen-Shin Lai),邱煌仁 | |
| dc.subject.keyword | 功因校正,升壓型轉換器,交錯控制,臨界導通, | zh_TW |
| dc.subject.keyword | power factor correction,boost converter,interleaved control,critical conduction, | en |
| dc.relation.page | 99 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-08-19 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電機工程學研究所 | zh_TW |
| 顯示於系所單位： | 電機工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-102-1.pdf 未授權公開取用 | 3.61 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。