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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳良基(Liang-Gee Chen) | |
| dc.contributor.author | Ping-Han Chuang | en |
| dc.contributor.author | 莊秉翰 | zh_TW |
| dc.date.accessioned | 2021-06-16T10:00:55Z | - |
| dc.date.available | 2017-02-08 | |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-11-14 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60173 | - |
| dc.description.abstract | 隨著傳統數位影像處理越來越成熟，另一個影像處理領域關於教導機器以人類的方式去看周遭世界的事物變得越來越熱門，這個領域就叫做電腦視覺。我們在第一章節介紹許多電腦視覺的應用，一些較低階的應用如物件辨識和語意切割，這些應用可以去實現更高階的應用，例如：智慧監視器系統，自動駕駛汽車，機器人，其中我們發現動作辨識是許多應用的核心技術，如果搭配動作辨識功能，攝影機可以分辨出緊急事件的發生已通報當局，自動駕駛汽車可以知道行人的速度已決定要加速或停下來，還有許多應用需要擁有動作辨識的功能，所以我們想要提供一個動作辨識的硬體架構去解決動作辨識所遇到的問題，讓電腦視覺領域再向前邁進。
我們瀏覽許多動作辨識相關的方法並將其分成三類。在瀏覽的過程中，我們發現兩個指標能判斷動作辨識系統的好壞，首先是辨識動作的準確度，再來是系統的執行速度，大部分的動作辨識方法可以得到蠻好的準確度，但是需要花費相當長的時間以致於無法即時運算，即使是處理低解析度的影片也是如此，我們在第一章節和第二章節詳細說明這個概念，而這也是為什麼我們要將動作辨識時坐在ASIC的原因，我們的目標是高幀率特徵抽取引擎應用在穿戴式裝置上，相關規格在第二章做定義，相較於其他類似的作品，我們的規格是最高的。 當我們比較過動作辨識中的特徵抽取方法後，我們決定採取HOG3D當作我們的特徵，但是原始的HOG3D演算法並不適合硬體實作，所以我們對不同參數做實驗以及更改演算法以適合硬體實作，這些內容在第三章節，有了這些結果之後我們在第四章節提出硬體架構設計，主要的貢獻在於移除演算法中非線性運算的部分使得更多資料可以重複使用，另外，也採用了平行運算的技巧去達到即時運算，和運算資源共享以減少硬體面積。在第四章節最後，我們分析晶片上記憶體和系統頻寬的取捨，也比較我們所提出的四種硬體架構設計。 | zh_TW |
| dc.description.abstract | With the traditional digital image processing technologies becoming more and more mature, another image processing field which is about teaching machines to see things in the real world like human doing has become more and more popular. This field is called computer vision. In chapter 1, we introduce a lot of application of computer vision. Some lower level applications are object recognition and semantic segmentation. These techniques make higher level applications like intelligent surveillance system, self-driving car and robot becomes realizable. We can find the fact that action recognition is a core key technique for these applications. With action recognition, surveillance can tell urgent events and call the authorities and self-driving car can know the speed of pedestrians to decide to accelerate or stop. So many fascinating applications need action recognition on them. So, we decide to provide a hardware architecture to solve the problems in action recognition to make advance in computer vision field.
We have surveyed lots of related work to recognize human actions and categorized these methods into three categories. During our survey of papers about action recognition, we find two critical issue to check whether an action recognition system is good enough. One is the accuracy of the system and the other is the processing time of the system. For most algorithms of action recognition, the accuracy of them is high enough while the processing time can not reach the real-time requirement even for low resolution video sequences. In chapter 1 and chapter 2, we state these concepts in detailed and they motivate us to implement action recognition on ASIC. Our target is a high frame rate feature extraction engine for wearable devices. The specification of our hardware is defined in chapter 2 and it is the highest specification compared with other similar works. After we compare some feature extraction methods for action recognition, we choose HOG3D descriptor as our feature. However, original algorithm of HOG3D descriptor is not hardware-friendly. Therefore, we do experiments to choose parameters and modify original HOG3D algorithm to make it more hardware-friendly in chapter 3. Following the results we get from chapter 3, we propose our architecture design in chapter 4. The main contribution comes from removing non-linear operations in algorithm making more data reuse. Besides, the technique of parallel computing and source sharing help to reach real-time requirement and reduce chip area. At last of chapter 4, we analysis the trade-off between on-chip memory and the bus bandwidth and compare engines of four versions we have proposed. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T10:00:55Z (GMT). No. of bitstreams: 1 ntu-105-R03943049-1.pdf: 3774154 bytes, checksum: 2cd8cabbcdf52da349c79b976316befe (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | The Authorization of Oral Members for Research Dissertation i
Acknowledgement iii Abstract in Chinese v Abstract vii Bibliography ix 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 The Applications of Computer Vision . . . . . . . . . . . . . 2 1.3 Motivation of Action Recognition ASIC . . . . . . . . . . . . 5 1.4 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . 10 2 Challenge of Action Recognition and HOG3D 11 2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Overview of Action Recognition Methods . . . . . . . . . . . 13 2.2.1 Human model based methods . . . . . . . . . . . . . 14 2.2.2 Holistic methods . . . . . . . . . . . . . . . . . . . . 15 2.2.3 Local feature methods . . . . . . . . . . . . . . . . . 18 2.3 Overview of HOG3D Engine . . . . . . . . . . . . . . . . . . 19 2.3.1 Comparison between HOG3D and other features . . . 19 2.3.2 Specification Definition . . . . . . . . . . . . . . . . . 20 2.3.3 Related Works of Hardware Architecture . . . . . . . 22 2.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 Proposed Robust Action Recognition System 25 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.2 System Overview . . . . . . . . . . . . . . . . . . . . . . . . 26 3.3 HOG3D Feature Extraction . . . . . . . . . . . . . . . . . . 29 3.3.1 3D Gradient Computation . . . . . . . . . . . . . . . 32 3.3.2 3D Orientation Quantization . . . . . . . . . . . . . . 32 3.3.3 Cell Histogram Computation . . . . . . . . . . . . . . 34 3.3.4 HOG3D Descriptor Computation . . . . . . . . . . . 34 3.4 Experiment Result . . . . . . . . . . . . . . . . . . . . . . . 34 3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 4 Proposed Architecture Design of HOG3D Descriptor 45 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4.2 Hardware Architecture of Direct Implementation . . . . . . . 48 4.2.1 Data Flow and Data Reuse . . . . . . . . . . . . . . 48 4.2.2 Direct Mapping from Algorithm to Architecture . . . 52 4.2.3 Report of Direct Implementation . . . . . . . . . . . 57 4.3 Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 58 4.3.1 Another Modification of HOG3D Algorithm . . . . . 58 4.3.2 Hardware Architecture of Optimized Implementation 60 4.3.3 Report of Optimized Implementation . . . . . . . . . 63 4.4 Analysis of Architectures with Data in DRAM . . . . . . . . 64 4.4.1 Architecture Modified from Direct Mapping . . . . . 65 4.4.2 Architecture Modified from Optimized Version . . . . 65 4.4.3 Comparison of Proposed Four Architectures . . . . . 66 4.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 5 Conclusion 69 Bibliography 73 | |
| dc.language.iso | en | |
| dc.title | 動作辨識之三維梯度方向直方圖架構設計 | zh_TW |
| dc.title | Architecture Design of Histograms of 3D Gradient Orientations for Action Recognition | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃朝宗(Chao-Tsung Huang),賴永康(Yong-Kang Lai),陳美娟(Mei-Juan Chen),叢培貴(Pei-Kuei Tsung) | |
| dc.subject.keyword | HOG3D特徵抽取,HOG3D特徵引擎,高幀率架構設計,資料重複使用設計,有效率面積優化架構, | zh_TW |
| dc.subject.keyword | HOG3D feature extraction,HOG3D feature engine,High frame rate architecture,Data reuse design,Area efficient architecture, | en |
| dc.relation.page | 80 | |
| dc.identifier.doi | 10.6342/NTU201603736 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-11-14 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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