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| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 黃天偉 | |
| dc.contributor.author | Feng-Yu Hsu | en |
| dc.contributor.author | 許峰毓 | zh_TW |
| dc.date.accessioned | 2021-06-16T09:59:56Z | - |
| dc.date.available | 2022-02-08 | |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-11-22 | |
| dc.identifier.citation | [1] F. van Rijs 'Status and trends of silicon LDMOS basestation PA technologies to go beyond 2.5 GHz applications', Radio Wireless Symp., pp.69 -72 Jan 2008
[2] R. Sorge , A. Fischer , A. Mai , P. Schley , J. Schmidt , C. Wipf , T. Mausolf , R. Pliquett , R. Barth and K. E. Ehwald 'Complementary RF LDMOS module for 12 V DC/DC converter and 6 GHz power applications', Silicon Monolithic Integr. Circuits in RF Syst., pp.57 -60, Jan 2011 [3] D. Gruner , R. Sorge , O. Bengtsson , A. Al Tanany and G. Boeck 'Analysis, design, [29]and evaluation of LDMOS FETs for RF power applications up to 6 GHz', IEEE Trans. Microw.Theory Techn., vol. 58, no. 12, pp.4022 -4030, Dec 2010 [4] T.Yan, H. Liao, Y. Z. Xiong, R. Zeng, J. Shi, and R. Huang, “Cost-effective integrated [30]RF power transistor in 0.18- m CMOS technology,” IEEE Electron Device Lett., vol. 27, no. 10, pp. 856–858, Oct. 2006 [5] G. Gonzalez, 2nd Ed., Microwave transistor amplifier analysis and design. Taiwan :Pearson Education [6] C. Cheng, 'Neutralization and Unilateralization,' in IRE Transactions on Circuit Theory, vol. 2, no. 2, pp. 138-145, Jun 1955. [7] H. Asada, K. Matsushita, K. Bunsen, K. Okada and A. Matsuzawa, 'A 60GHz CMOS power amplifier using capacitive cross-coupling neutralization with 16 % PAE,' Microwave Integrated Circuits Conference (EuMIC), 2011 European, Manchester, 2011, pp. 554-557. [8] David M. Pozar, Microwave Engineering, 3rd Edition, John Wiley & Sons, Inc., Hoboken, New Jersey, 2005. [9] S. Venkateswaran, 'An invariant stability factor and its physical significance,' in Proceedings of the IEE - Part C: Monographs, vol. 109, no. 15, pp. 98-, March 1962. [10] K. Onizuka, H. Ishihara, M. Hosoya, S. Saigusa, O. Watanabe and S. Otaka, 'A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion,' in IEEE Journal of Solid-State Circuits, vol. 47, no. 8, pp. 1820-1827, Aug. 2012. [11] I. Aoki, S. Kee, D. Rutledge, and A. Hajimiri, “Fully integrated CMOS power amplifier design using the distributed active-transformer architecture,” IEEE J.Solid-State Circuits, vol. 37, no. 3, pp. 371–383, Mar. 2002. [12] H. Jeon et al., 'A Cascode Feedback Bias Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology,' in IEEE Transactions on Microwave Theory and Techniques, vol. 61, no. 2, pp. 890-901, Feb. 2013 [13] S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi and P. M. Asbeck, 'A Watt-Level Stacked-FET Linear Power Amplifier in Silicon-on-Insulator CMOS,' in IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 1, pp. 57-64, Jan. 2010. [14] C.Wang, M. Vaidyanathan, and L. E. Larson, “A capacitance-compensation technique for improved linearity in CMOS class-AB power amplifiers, ”IEEE J. Solid-State Circuits, vol. 39, no. 11, pp. 1927–1937,Nov. 2004. [15] J. Kim et al., “A fully-integrated high-power linear CMOS power amplifier with a parallel-series combining transformer,” IEEE J. Solid-State Circuits, vol. 47, no. 3, pp. 599–614, Mar. 2012 [16] I. Aoki, S. D. Kee, D. B. Rutledge and A. Hajimiri, 'Distributed active transformer a new power-combining and impedance-transformation technique', IEEE Trans.Microw. Theory Tech., vol. 50, no. 1, pp.316 -331 2002. [17] P. Haldi , D. Chowdhury , P. Reynaert , G. Liu and A. M. Niknejad “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS”, IEEE J. Solid-State Circuits, vol.43,no.5,pp.1054-1063, May 2008. [18] B. Koo, T. Joo, Y. Na, and S. Hong, “A fully integrated dual-mode CMOS power amplifier for WCDMA applications,” in Int. Solid-State Circuits Conf., 2012, pp. 82–84. [19] K. Wang, M. Jones and S. Nelson, 'The S-probe-a new, cost-effective, 4-gamma method for evaluating multi-stage amplifier stability,' in Microwave Symposium Digest, 1992., IEEE MTT-S International, Albuquerque, NM, USA, 1992, pp. 829-832 vol.2. [20] J.-W. Lai and A. Valdes-Garcia, 'A 1V 17.9dBm 60GHz Power Amplifier in Standard 65nm CMOS,' ISSCC Dig. Tech. Papers, pp. 424-425, Feb. 201 [21] Maryam Fathi, David K. Su, Bruce A. Wooley, “A 30.3dBm 1.9GHz-bandwidth 2×4-array stacked 5.3GHz CMOS power amplifier”, Int. Solid-State Circuits Conf. Tech. Dig., Feb 2013. [22] M. Fathi, D. K. Su, and B. A. Wooley, “A stacked 6.5-GHz 29.6-dBm power amplifier in standard 65-nm CMOS,” in Proc. IEEE Custom Integr. Circuits Conf., Sep. 2010, pp. 1–4. [23] P. Haldi, D. Chowdhury, P. Reynaert, G. Liu and A. M. Niknejad “A 5.8 GHz 1 V linear power amplifier using a novel on-chip transformer power combiner in standard 90 nm CMOS”, IEEE J. Solid-State Circuits, vol.43,no.5,pp.1054-1063, May 2008. [24] K.-Y. Kao,et al.,“Phase-Delay Cold-FET Pre-Distortion Linearizer for Millimeter-Wave CMOS Power Amplifiers,” IEEE Trans. Microw. Theory Techn., vol. 61, no. 12, pp.4505–4519,Dec.2013. [25] J.-H. Tsai, et al., “A 60 GHz CMOS power amplifier with built-in pre-distortion linearizer,” IEEEMicrow. Wireless Compon. Lett.,vol. 21, no. 12, pp. 676–678, Dec.2011. [26] 葉景富撰，三維架構之雙輻射狀功率合成技術之研究，國立台灣大學電信工程研究所博士論文，2015 年 3 月。 [27] Tzu-Yuan Huang, Yu-Hsuan Lin and Huei Wang, 'A K-Band adaptive-bias power amplifier with enhanced linearizer using 0.18-µm CMOS process,' Microwave Symposium (IMS), 2015 IEEE MTT-S International, Phoenix, AZ, 2015, pp. 1-3. [28] J. W. Lee , et al., 'A 27 GHz, 14 dBm CMOS power amplifier using 0.18 J.lm common-source MOSFETs,' IEEE Microw. And Wireless Compon. Lett., vol. 18, pp. 755-757, Nov. 2008. [29] H. Portela, et al., 'Fully integrated high efficiency K-band PA in 0.18-J.lm CMOS technology,' in Proc. Microwave and Optical Conference, Nov. 2009, pp. 393-396 [30] 黃梓原撰，微波及毫米波系統關鍵元件之設計與研究，國立台灣大學電信工程研究所碩士論文，2015 年 2 月。 [31] 羅士竣撰，具三維結構之瓦級並聯-並聯變壓器結合式CMOS功率放大器之研製，國立台灣大學電信工程研究所碩士論文，2015 年 7 月 [32] J. F. Yeh, J. H. Cheng, J. H. Tsai and T. W. Huang, 'A 57–66 GHz power amplifier with a linearization technique in 65-nm CMOS process,' Microwave Conference (EuMC), 2014 44th European, Rome, 2014, pp. 1253-1256. doi: 10.1109/EuMC.2014.6986670 | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60158 | - |
| dc.description.abstract | 隨著無線通訊系統的發展以及半導體製程的演進，以互補式金氧半場效電晶體實現射頻電路以成本優勢逐漸成為市場焦點，其中功率放大器為收發機中最關鍵的電路之一，本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。
論文的第二章描述了一個以40奈米橫向雙擴散金氧半場效電晶體製程實現一個1.93-GHz的功率放大器。為了增加功率輸出，採用變壓器電路架構來完成輸出端阻抗匹配，並使用差動電路的架構及中和電容，減少閘級和汲級端的寄生電容，晶片面積為0.620 mm2，此電路達到輸出功率23.1dBm。 論文的第三章描述了以40奈米橫向雙擴散金氧半場效電晶體實現一個5-GHz高輸出功率變壓器結合式放大器，透過電流-電流結合變壓器的技術，將多個變壓器實現在同一區域減少所需要的面積，且有相當好的阻抗平衡，此外還使用放射狀三維架構，減少多路結合需要的面積，進一步將晶片面積縮小。 論文的第四章描述了一個以65奈米互補式金氧半場效電晶體製程實現的29-GHz功率放大器，採用預失真線性化電路並以變壓器電路架構來完成阻抗匹配。此功率放大器使用預失真線性化電路可以改善輸出功率1 dB 壓縮點，進而提升此功率放大器的線性操作範圍。 關鍵字:功率放大器、變壓器結合、高電壓操作、線性化功率放大器 | zh_TW |
| dc.description.abstract | With the development of wireless communication and the evolution of semiconductor process, the radio frequency integrated circuits implemented in CMOS technology become the key point in the industry with low cost advantage. The power amplifier is the most critical component in the transceiver design. Thus the main focus of this thesis is the design and analysis of CMOS power amplifier [31].
The chapter 2 describes a 4G-LTE power amplifier, which is implemented in 40 nm laterally diffused metal oxide semiconductor (LDMOS) CMOS process. To increase the output power, the circuit uses transformer-based matching network for input and output. The proposed PA is designed in a differential common source structure. The neutralization technique is also implemented in this PA design to reduce the intrinsic capacitance from drain to gate. The chip size of the PA is 0.62mm2 and the output saturation power achieves 23.1dBm. The chapter 3 describes a fully-integrated Wi-Fi power amplifier, which is implemented in 40 nm LDMOS process. By current-current combining transformer technique, the multiple transformers can be realized in a compact area with similar port impedance. In addition, the PA uses 3-D radial architecture to reduce the area of multi-way combining. The chapter 4 describes a 29 GHz power amplifier in 65 nm CMOS process. In this work, the PA is designed with pre-distortion linearizer and the circuit uses transformer-based matching networks for input and output network. This power amplifier improves the OP1dB and linearity. Index term-Power amplifier, Transformer combining, High operating voltage, Pre-distortion power amplifier | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T09:59:56Z (GMT). No. of bitstreams: 1 ntu-105-R03942004-1.pdf: 9633761 bytes, checksum: fc1c175004cdc574427b0398903f1b8b (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 口試委員會審定書 ........................................................................................................... i
誌謝 .................................................................................................................................. ii 中文摘要......................................................................................................................... iii ABSTRACT .................................................................................................................... iv CONTENTS ......................................................................................................................v LIST OF FIGURES....................................................................................................... viii LIST OF TABLES......................................................................................................... xiii Chapter 1 Introduction .........................................................................................1 1.1 Motivation .........................................................................................................1 1.2 Thesis organization............................................................................................1 Chapter 2 A 1.93 GHz Power Amplifier ..............................................................2 2.1 Introduction .......................................................................................................2 2.2 LDMOS Introduction ........................................................................................2 2.3 Power Combining Techniques...........................................................................6 2.3.1 Direct Combining.........................................................................................6 2.3.2 Wilkinson Combining ..................................................................................7 2.3.3 Transformer Combining ...............................................................................8 2.4 Circuit Design....................................................................................................9 2.4.1 Circuit Architecture ......................................................................................9 2.4.2 Devices and Bias Selections.......................................................................10 2.4.3 Transformer Design....................................................................................14 2.4.4 Neutralization Technique ...........................................................................21 2.4.5 1.93 GHz Power Amplifier.........................................................................26 2.5 Simulation Results...........................................................................................27 2.5.1 S-parameter Simulation..............................................................................28 2.5.2 Large-signal Simulation .............................................................................30 2.6 Experimental Results and Discussion .............................................................31 Chapter 3 A Fully-Integrated 5 GHz Power Amplifier with Current-Current Transformer Combining and 3-D Structure .......................................................35 3.1 Introduction .....................................................................................................35 3.2 Transformer-Based Power Combining Techniques .........................................35 3.2.1 TF-Based Voltage Combining (Series combining) ....................................35 3.2.2 TF-Based Current Combining (Parallel-Combining).................................38 3.2.3 Current- Current Combining Transformer (Parallel- Parallel Combining)39 3.3 Circuit Design..................................................................................................41 3.3.1 Circuit Architecture ....................................................................................41 3.3.2 Devices and Bias Selections.......................................................................43 3.3.3 Transformer Design....................................................................................44 3.3.4 Power-stage Design....................................................................................49 3.3.5 Two–stage 5 GHz Current-Current Combining Transformer Power Amplifier .................................................................................................................50 3.4 Simulation Results...........................................................................................52 3.4.1 S-parameter Simulation..............................................................................52 3.4.2 Large-signal Simulation .............................................................................53 3.5 Experimental Results and Discussion .............................................................54 Chapter 4 A 29 GHz Power Amplifier with Pre-Distortion Linearizer ..........60 4.1 Introduction .....................................................................................................60 4.2 Implementation of Enhanced Linearizer to Power Amplifier Conclusions.....60 4.2.1 Introduction of the Pre-Distortion Linearization........................................60 4.2.2 Implementation of Pre-Distortion Linearizer .............................................61 4.2.3 Analysis of IM3 Cancellation by the Pre-distortion Linearizer .................63 4.3 Circuit Design..................................................................................................64 4.3.1 Circuit Architecture ....................................................................................64 4.3.2 Devices and Bias Selections.......................................................................66 4.3.3 Transformer Design....................................................................................68 4.3.4 A 29 GHz Power Amplifier with Pre-Distortion Linearizer ......................73 4.4 Simulation Results...........................................................................................73 4.4.1 S-parameter Simulation..............................................................................73 4.4.2 Large-signal Simulation .............................................................................75 Chapter 5 Conclusions ........................................................................................80 REFERENCE ..................................................................................................................82 | |
| dc.language.iso | en | |
| dc.title | 40奈米LDMOS多路變壓器結合及65奈米CMOS預失真線性器功率放大器之研製 | zh_TW |
| dc.title | Research of 40nm LDMOS Multi-Way Transformer Combined and 65nm CMOS Pre-Distortion Linearized Power Amplifier | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 蔡政翰,邱煥凱 | |
| dc.subject.keyword | 功率放大器,變壓器結合,高電壓操作,線性化功率放大器, | zh_TW |
| dc.subject.keyword | Power amplifier,Transformer combining,High operating voltage,Pre-distortion power amplifier, | en |
| dc.relation.page | 84 | |
| dc.identifier.doi | 10.6342/NTU201603754 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-11-23 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電信工程學研究所 | zh_TW |
| Appears in Collections: | 電信工程學研究所 | |
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| ntu-105-1.pdf Restricted Access | 9.41 MB | Adobe PDF |
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