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| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 李建模(Chien-Mo Li) | |
| dc.contributor.author | Yu-Wei Chen | en |
| dc.contributor.author | 陳佑維 | zh_TW |
| dc.date.accessioned | 2021-06-16T09:58:52Z | - |
| dc.date.available | 2018-02-08 | |
| dc.date.copyright | 2017-02-08 | |
| dc.date.issued | 2016 | |
| dc.date.submitted | 2016-12-07 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60142 | - |
| dc.description.abstract | 生成壓縮的測試集對於降低測試成本是非常重要的。在此論文中，我們提出了一種新的測試壓縮演算法，可以實現高度的壓縮，稱為平行次序動態測試壓縮(Parallel Order Dynamic Test Compaction)。我們的結果顯示，在單個測試向量生產的過程中，次級故障的次序對於測試壓縮是非常重要的。我們使用GPU去同時執行許多不同次序的次級故障，並選擇測試到最大故障數量的最佳測試向量。實驗結果顯示，我們的測試長度比高度壓縮的商業自動測試向量產生器短40%，我們的測試長度是迄今為止所有以前發佈過的方法中最小的。我們的結果顯示，我們的技術也有助於壓縮N次偵測的測試集。在N=3、N=5、N=8中，我們的測試長度至少比商業自動測試向量產生器短了四分之一。 | zh_TW |
| dc.description.abstract | Generating a compacted test set is very important to reduce the cost of testing. In this thesis, we proposed a novel test compaction algorithm which achieve high compaction, called Parallel Order Dynamic Test Compaction (PO-DTC). Our results show that the order of secondary faults within a single test generation is very important for test compaction. We use GPU to launch many parallel ATPG with different orders of secondary faults. Then we choose the best test pattern, which detects the largest number of faults. Experimental results show that our test length is 40% shorter than that of a highly compacted commercial ATPG. Our test length is the smallest among all previous work published so far. Our results show that our technique is also useful to compact N-detect test sets. Our test length is at least 1/4 short than that of the commercial ATPG for N=3, N=5, N=8. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T09:58:52Z (GMT). No. of bitstreams: 1 ntu-105-R03943143-1.pdf: 1953548 bytes, checksum: 97fe4f87d065f9c55241e7a492032d29 (MD5) Previous issue date: 2016 | en |
| dc.description.tableofcontents | 致謝 i
摘要 ii Abstract iii Table of Contents iv List of Figures v List of Tables vi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Proposed Technique 5 1.3 Contribution 6 1.4 Organization 8 Chapter 2 Background 9 2.1 Dynamic Test Compaction 9 2.1.1 Primary Fault Order of Dynamic Test Compaction 9 2.1.2 Secondary Fault Selection of Dynamic Test Compaction 11 2.2 Static Test Compaction 12 2.3 N-detect Test Set Compaction Algorithm 13 2.4 Parallel Programming Techniques for ATPG 13 Chapter 3 Proposed Techniques 15 3.1 Overall Flow 15 3.2 Parallel Order Dynamic Test Compaction 16 3.3 GPU-based Test Generation (SWK algorithm) 19 3.3.1 Signal Representation 20 3.3.2 Initialize Objectives 21 3.3.3 Backtrace 22 3.3.4 Propagation 23 3.3.5 Success or Time Out 24 3.3.6 Example of implementation for PO-DTC 25 Chapter 4 Experimental Results 30 4.1 Compare with the baseline ATPG 31 4.2 Compare with Previous Methods and the Commercial ATPG Tool 32 4.3 N-detect Test Set Comparison 34 4.4 Comparison of using different numbers of blocks 36 Chapter 5 Conclusion and Future work 37 References 38 | |
| dc.language.iso | en | |
| dc.subject | 測試壓縮 | zh_TW |
| dc.subject | 平行化自動測試向量產生器 | zh_TW |
| dc.subject | parallel ATPG | en |
| dc.subject | test compaction | en |
| dc.title | 針對測試壓縮的平行次序自動測試向量產生器 | zh_TW |
| dc.title | Parallel Order Automatic Test Pattern Generation
for Test Compaction | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 105-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 黃俊郎,呂學坤 | |
| dc.subject.keyword | 平行化自動測試向量產生器,測試壓縮, | zh_TW |
| dc.subject.keyword | parallel ATPG,test compaction, | en |
| dc.relation.page | 42 | |
| dc.identifier.doi | 10.6342/NTU201603794 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2016-12-08 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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