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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 郭大維(Tei-Wei Kuo) | |
dc.contributor.author | Ming-Chang Yang | en |
dc.contributor.author | 楊明昌 | zh_TW |
dc.date.accessioned | 2021-06-16T09:56:51Z | - |
dc.date.available | 2020-02-08 | |
dc.date.copyright | 2017-02-08 | |
dc.date.issued | 2016 | |
dc.date.submitted | 2016-12-23 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/60112 | - |
dc.description.abstract | 在過去的數十年中,快閃記憶體和硬碟已經幾乎主宰了整個儲存市場。為了能替接下來的大數據時代開創超大規模的儲存容量,許多不同的技術已經開始被應用於超大型儲存容量之快閃記憶體儲存裝置和硬碟中。本博士論文探討,當儲存系統規模上升時,所可能面臨之新的設計挑戰;同時,為了避免持續複雜化現有之設計以及造成較大開發成本和較長的開發時間,本論文更企求能透過提出新管理層之設計理念,用更模組化和更符合經濟效益的方式來解決所觀察到的問題。首先,我們重新審視快閃記憶體儲存裝置之軟體管理層設計,並提出將蘊含高度存取平行的快閃記憶體晶片重組並虛擬為可靠度較高的「虛擬快閃記憶體晶片」,藉此提升資料的可修復率。接著,我們探討如何能有效達成好的設計可延展性,以促進當快閃記憶體儲存裝置規模提升時的開發效率。不同於提出另一個設計架構,我們提出一個新軟體層設計來有效提升多晶片和多控制單元快閃記憶體儲存裝置之效能可延展性。另一方面,本論文也探討了疊瓦式磁記錄技術之設計挑戰,因為該技術能在不改變傳統硬碟的基本架構下有效地提升硬碟之儲存空間密度。本論文提出一個新軟體層設計來解決主機感知式疊瓦式磁記錄硬碟所可能產生的長延遲效應;此設計不僅保留了主機感知式疊瓦式磁記錄硬碟之較為經濟的設計模型,並彈性地利用主機端的計算和管理資源來提升硬碟之效能。 | zh_TW |
dc.description.abstract | Flash-memory and Hard Disk Drives (HDDs) have almost dominated the whole spectrum of storage markets in the past decades. In order to further enable ultra-scale storage capacity for the coming big data era, various technologies are adopted in the designs of ultra-scale flash storage devices and huge-capacity HDDs. This dissertation investigates the emerging challenges when the storage systems are scaled up. We aim to enable new layer designs to resolve the observed challenges in a modular and cost-effective way, instead of further complicating the existing designs. In this dissertation, we first rethink the layer design of flash devices and propose a complete paradigm shift to re-configure physical flash chips of potentially massive parallelism into better “virtual chips,”' so as to improve the data recoverability. Then, we investigate how to achieve good design scalability to facilitate the device development when the scale of flash devices keeps growing. We present a new layer design to improve the performance scalability for flash devices consisting of a large number of flash chips and many cores, without redesigning another new architecture. On the other hand, this dissertation also investigates the Shingled Magnetic Recording (SMR) technology, because SMR technology can effectively increase the areal density for the conventional HDDs. In particular, we presents a novel layer design to remedy the long latency behavior of the Host-Aware Shingled Magnetic Recording (HA-SMR) drive. Our design not only maintains the cost-effective model of the existing HA-SMR drives, but also integrates the computing and management resources of the host system to improve the drive performance when needed. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T09:56:51Z (GMT). No. of bitstreams: 1 ntu-105-D02944016-1.pdf: 5107316 bytes, checksum: f57dda66bc148c848febc71104dad691 (MD5) Previous issue date: 2016 | en |
dc.description.tableofcontents | Abstract in Chinese vii
Abstract ix Acknowledgment xi Contents xiii List of Figures xvii List of Tables xviii 1 Introduction 1 1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Background and Related Work . . . . . . . . . . . . . . . . . . . . . . . 4 1.2.1 Flash-memory-based Storage Devices . . . . . . . . . . . . . . . 4 1.2.2 Shingled Magnetic Recording (SMR) Drives . . . . . . . . . . . 7 1.3 Objectives and Contributions . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 Virtual Flash Chip Layer: Improve the Data Recoverability of Flash Devices 14 2.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2 A Virtualized HAL Design for Virtual Flash Chips . . . . . . . . . . . . 18 2.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2.2 The Virtual Chip Organization . . . . . . . . . . . . . . . . . . . 20 2.2.3 Stack-based Error Correction . . . . . . . . . . . . . . . . . . . . 25 2.2.4 Analysis of 2D Parity Protection . . . . . . . . . . . . . . . . . . 30 2.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 2.3.1 Evaluation Metrics and Experiment Setup . . . . . . . . . . . . . 34 2.3.2 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . 36 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 3 Scalable Redirection Layer: Improve the Performance Scalability of Enterprise-Scale Flash Devices 43 3.1 Architecture Change and Motivation . . . . . . . . . . . . . . . . . . . . 43 3.2 Scalable Redirection Layer . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 3.2.2 Request Redirection Policy . . . . . . . . . . . . . . . . . . . . . 49 3.2.3 Challenges and Practical Implementations . . . . . . . . . . . . . 52 3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.1 Evaluation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.3.2 Evaluation Results . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 4 Virtual Persistent Cache Layer: Remedy the Long Latency Behavior of HA-SMR Drives 63 4.1 Background and Motivation . . . . . . . . . . . . . . . . . . . . . . . . 63 4.1.1 Host-Aware SMR Drive Model . . . . . . . . . . . . . . . . . . . 63 4.1.2 Long Latency Behavior of Persistent Cache . . . . . . . . . . . . 66 4.1.3 Update Frequency Investigation . . . . . . . . . . . . . . . . . . 69 4.1.4 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2 Virtual Persistent Cache . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.2.2 Data Redirection in Virtual Persistent Cache . . . . . . . . . . . . 73 4.2.3 Challenges and Practical Solutions . . . . . . . . . . . . . . . . . 78 4.2.4 Optimization Opportunities . . . . . . . . . . . . . . . . . . . . 83 4.3 Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.1 Evaluation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . 84 4.3.2 Evaluation Results . . . . . . . . . . . . . . . . . . . . . . . . . 86 4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 5 Concluding Remarks 94 Bibliography 96 Curriculum Vitae 107 Publication List 108 | |
dc.language.iso | en | |
dc.title | 基於超大規模儲存系統之新管理層設計 | zh_TW |
dc.title | Enabling New Layer Designs for Ultra-Scale Storage Systems | en |
dc.type | Thesis | |
dc.date.schoolyear | 105-1 | |
dc.description.degree | 博士 | |
dc.contributor.coadvisor | 張原豪(Yuan-Hao Chang) | |
dc.contributor.oralexamcommittee | 黃彥男(Yen-Nun Huang),徐慰中(Wei-Chung Hsu),薛智文(Chih-Wen Hsueh),施吉昇(Chi-Sheng Shih),洪士灝(Shih-Hao Hung) | |
dc.subject.keyword | 超大規模,儲存系統,新管理層,虛擬化儲存,快閃記憶體,虛擬快閃記憶體,資料可回覆性,可擴展之再定向,多快閃記憶體晶片,多控制單元,快閃記憶體模組,效能可擴展性,主機可感知式,疊瓦式磁記錄硬碟,持續快取,長延遲現象,虛擬持續快取,效能提升, | zh_TW |
dc.subject.keyword | ultra-scale,storage system,new layer design,storage virtualization,flash memory,virtual flash chip,data recoverability,scalable redirection,multi-chip,multi-core,flash module,performance scalability,host-aware,shingled magnetic recording,persistent cache,long latency behavior,virtual persistent cache,performance improvement, | en |
dc.relation.page | 111 | |
dc.identifier.doi | 10.6342/NTU201603829 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2016-12-23 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 資訊網路與多媒體研究所 | zh_TW |
顯示於系所單位: | 資訊網路與多媒體研究所 |
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