非同步時脈之以零點交越偵測器為基礎的增量型三角積分類比數位轉換器的分析與設計

Abstract

增量型三角積分調變器適合應用於逐個樣本採樣之應用，舉凡測量儀器、感測器皆為其應用範圍。這些應用通常需要高精準度、低功耗之規格。 傳統增量型三角積分調變器之積分器實現方式，會使用一個具高增益且有頻寬需求之開迴路放大器，去實現一閉迴路之高精準積分器。然而，放大器會以最差之狀況去設計頻寬，導致短積分時間需求之週期於積分完成後進入穩定狀 態，需等到下一個由時脈產生器產生之週期性時脈來臨時，才能驅使下一個週期繼續進行，如此便造成放大器穩態時的功率消耗與許多時間的浪費。 本篇論文提出一非同步週期之增量型三角積分調變器。積分器以一連續時間之比較器與一電流源實現，能在一周期積分完成後，立刻觸發下一周期的進行，並於一次完整採樣轉換週期結束後將電路完整關閉，達到快速及省電的效果。 本晶片採用聯電二八奈米互補式金屬氧化物半導體1P7M製程。本晶片轉換率為每秒40次採樣，並於二十赫茲之有效頻寬下得到71 dB之訊號雜訊失真比。在1.8伏特之電源供應下總共消耗141.1奈瓦。晶片的核心面積小於0.105平方毫米。

Incremental delta-sigma data converter (IDC) is used for applications of sample-by-sample conversion, including instrumentation measurement and sensor applications. Therefore, the requirement of both high resolution and low power consumption are necessary. For a traditional IDC, the integrator used to be realized by opamps (OPA). However, the OPA bandwidth is designed to fit the worst case of the biggest input signal. For an small input signal, little time is needed to be well-integrated, and the OPA gets into steady state. The OPA has to hold the output until the next clock stage comes. Therefore, lots of time and steady state power of OPA are wasted. In this thesis, we present an asynchronous incremental delta-sigma converter to deal with the problem mentioned above. A continuous-time comparator and a current source are used to realize an integrator. The next cycle will be triggered right after the current cycle of integration is completed. After several cycles of an conversion are completed, the ADC is then power down. This integration method is not only fast but power saving. Fabricated in UMC 28 nm CMOS HPC-PLUS 1P7M technology, the conversion rate of the proposed modulator is 40 S/s. It achieves peak SNDR of 71 dB with the signal bandwidth of 20 Hz and power consumption of 141.1 nW. The active area of this modulator occupies less than 0.105 mm^2.