低功耗電阻式記憶體之元件設計與其特性研究

Abstract

近來,由於非揮發性記憶體技術的快速發展,使數位科技產業如手機、顯示 器面板、USB、數位相機、電腦等產品都發生了巨大的變革。然而,快閃記憶體 為了達到更好的效能,在製程尺度不斷微縮之下,將面臨非常大的挑戰。為了提 供未來的電子元件在應用上能有更多可兼容的記憶記憶體元件,在各種新穎的記 憶體研究當中,電阻式記憶體(RRAM)由於擁有較高操作速度、有效降低功耗、高 耐用性和 CMOS 兼容性等優點,是最有希望可以在未來取代快閃記憶體之新記憶 體元件。更重要的是,由於 RRAM 簡單的結構,使其可以整合至 3D 水平(3D-HRAM) 和垂直(3D-VRAM)交叉記憶體陣列中,用以實現較高的存儲密度。儘管有多項優 點,RRAM 的技術仍未取代主流之快閃記憶體元件,主要是因為目前 RRAM 的功 耗及可靠性問題、較小的記憶視窗和記憶體陣列中之漏電流問題。因此,本論文 研究主要是通過以下三種不同的元件設計來提高 RRAM 記憶體之元件特性。 1. 基於氧離子之 push-pull 機制實現記憶體開關和臨限開關之雙功能電阻式開關 元件 利用過渡金屬氧化物實現同時擁有非揮發性記憶體開關和揮發性臨限開 關之功能,在交叉記憶體陣列中具有極大的潛力可以取代快閃記憶體元件。 此實驗中我們利用(非晶 TiOx)/(Ag 奈米顆粒)/(多晶 TiOx)作為電阻式開關層並 結合 ITO 上電極以及表面粗糙化的 FTO 下電極實出記憶體開關和臨限開關之 功能。元件具有不需要forming 過程可避免元件受到大電壓操作而受到破壞, 且元件俱有較低的操作電壓(< ±1 V)及自我限制電流(<50 μA)的功能,使元件 具有避免產生永久性崩潰之低功耗操作。當元件操作在臨限開關模式(Selector device),此時元件同樣俱有較低的操作電壓(< ±1 V)及較低的臨限開關電流 (-Ith = -2 μA and Ith = 0.1 μA, at -Vth = -0.8 V and Vth = 0.4 V)之特性,此優良的特 性有利於改善交叉式記憶體陣列之選擇性並有效抑制漏電流問題。 2. 藉由侷限導電絲的形成以實現低功耗之電阻式記憶體 為了進一步改善上述電阻式記憶體元件之功耗、記憶視窗、穩定度及可靠 度問題。此實驗中我們利用(TiOx)/(Ag 奈米顆粒)/(TiOx)/(AlTiOx)作為電阻式開 關層並結合 ITO 上電極以及表面粗糙化的 FTO 下電極,以實現優良之電阻式 記憶體特性。此電阻式記憶體元件具有較低的操作電壓(<±1 V)、低功耗(Pset = 〜10 μW 和 Preset = 〜0.65 μW)、較低的電阻變化率(HRS 和 LRS 的相對波動 率為 3.5 %和 7.6%)、可靠資料儲存以及較大的記憶視窗(〜300)。由於此元 件中使用了穩定的 AlTiOx 阻擋層來限制導電絲形成的數目,因此此元件極具 明顯功耗降低之特性。 3. 利用石墨烯和六方氮化硼異質結構設計垂直架構之電阻式記憶體元件 由於 3D 水平交叉記憶體陣列(3D-HRAM)在每一層的堆疊中需要關鍵的黃 光微影技術,並且這種製造成本會隨著堆疊數量呈現線性增加。因此,在此 實驗中,我們證實了利用石墨烯水平平面電極/多層六方氮化硼絕緣介電質堆 疊層、AlOx/TiOx 電阻式開關層以及 ITO 垂直柱狀電極組成的二維材料垂直 RRAM 結構可展現出可靠的記憶體元件特性,包含極低的功耗(Pset = 〜2 μW, Preset = 〜0.2 μW)及較大記憶視窗(> 300)。由於利用超薄(~2 nm)且絕緣及本身 高導熱特性之六方氮化硼,我們提出二維材料垂直 RRAM 結構經由增加堆疊 的層數,相信對未來的超高密度記憶體元件和黃光微影的成本降低具有巨大 的潛力。

Recently, the rapid development of nonvolatile memory technology has enabled a great revolution of digital technology including mobile phone, display panel, USB flash drivers, digital cameras and computer. However, the charge-based flash memories will face formidable device scaling challenges. In order to have more compatible storage devices for future electronic device applications, resistive random access memory (RRAM) is the most promising candidate to replace the charge-based flash memories due to its advantages, such as high-speed operation, low power consumption, high endurance, and CMOS compatible. More importantly, the simple structure of RRAM makes it feasible to be integrated into the 3D horizontal (3D-HRAM) and vertical (3D-VRAM) cross-point arrays to realize the high storage density. Nonetheless, RRAM technology has not yet begun to replace the mainstream flash technology which is mainly delayed by programing power consumption, small memory window, poor reliability and serious sneak current problems in the crossbar memory arrays. Therefore, the objective of the research is to improve the performance of the RRAM devices by several reliable designs as below. 1. Dual-functional Memory and Threshold Resistive Switching Based on the Push-Pull Mechanism of Oxygen Ions The combination of nonvolatile memory switching and volatile threshold switching functions of transition metal oxides in crossbar memory arrays is of great potential for replacing charge-based flash memory in very-large-scale integration. Here, the resistive switching material structure, (amorphous TiOx)/(Ag nanoparticles)/(polycrystalline TiOx), fabricated on the textured-FTO substrate with ITO as the top electrode exhibits both the memory switching and threshold switching functions. When the device is used for resistive switching, it is forming-free for resistive memory applications with low operation voltage (<±1V) and self-compliance to current up to 50 μA. Therefore, the operation voltage and current are significantly reduced. When it is used for threshold switching, the low threshold current (-Ith = -2 μA and Ith = 0.1 μA, at -Vth = -0.8 V and Vth = 0.4 V) is beneficial for improving the sneak current problem in crossbar memory arrays. 2. Low-Power Resistive Random Access Memory by Confining the Formation of Conducting Filaments In order to further improve the power consumption, memory window, uniformity and reliability of RRAM device in section 1, a resistive switching material structure, TiOx/silver nanoparticles/TiOx/AlTiOx, fabricated between the fluorine-doped tin oxidebottom electrode and the indium tin oxide top electrode is demonstrated. The device exhibits excellent memory performances, such as low operation voltage (<±1 V), low operation power (Pset = ~10 μW and Preset = ~0.65μW), small variation in resistance (The relative fluctuations of HRS and LRS are 3.5% and 7.6%), reliable data retention, and a large memory window (~300). The stable bottom AlTiOx barrier layer in the device structure limits the formation of conducting filaments; therefore, the current and power consumption of device operation are significantly reduced. 3. Graphene/h-BN Heterostructures for Vertical Architecture of RRAM Design Because the 3D-HRAM requires critical lithography and other process for every stacked layer, and this fabrication cost overhead increases linearly with the number of stacks. Here, it is demonstrated that the 2D materials-based vertical RRAM structure composed of graphene plane electrode/multilayer h-BN insulating dielectric stacked layers, AlOx/TiOx resistive switching layer and ITO pillar electrode exhibits reliable device performance including forming-free, low power consumption (Pset = ~2 μW and Preset = ~0.2 μW), and large memory window (> 300). Owing to the ultrathin-insulating dielectric layer (~2 nm) and naturally high thermal conductivity characteristics of h-BN, the proposed vertical RRAM exhibits huge potential for future ultra high-density memory integration and per-bit lithography cost reduction by increasing the stacked layers.