應用於快速合成微波及毫米波積體電路之新式演化式演算法

Abstract

無線通訊晶片在智慧型手機等高科技產品上扮演著不可或缺的角色。隨著技術快速演進，工程師如何在短時間內設計出高效能的晶片是決定著自身及產業競爭力的關鍵。本篇論文以演化式計算實作微波及毫米波電路的匹配網路自動合成及最佳化，實現了商用模擬軟體缺乏的電路合成功能。在平行計算的加速之下，可在數秒內輕易地完成匹配網路的最佳設計。 論文的第一部分說明如何使用先進的演化式計算去合成匹配網路。有別於過去在微波領域發表過的文獻，我們深入探討匹配網路合成的特性並結合電腦科學領域的先進技術，針對匹配網路設計特別實作出更快且精確的合成演算法，使工程師能夠在不需分析匹配網路架構下設計出高效能的電路。最後以電腦實驗統計提出的演算法的優異效能，如放大器及濾波器電路合成。 第二部分展示用提出的演算法實作的兩個寬頻放大器。首先是增益頻寬第一個涵蓋整個D-band的65-nm CMOS寬頻放大器，我們針對級間網路設計一個最佳化方法來決定所需的放大器級數，並且合成各個寬頻的匹配網路，此外也探討了改善疊接式放大器匹配的方法。而第二個電路是使用0.1-μm GaAs pHEMT製程實作的寬頻Ka-band功率放大器，由於最佳化的匹配網路使得增益、反射損耗、輸出功率及效率能夠有良好的寬頻表現。

This thesis presents a novel algorithm for microwave circuit synthesis and optimization, which is not presented in the current commercial circuit-simulation software. With the help of our proposed algorithm, the time for the design of matching networks can be reduced to only a few seconds. Our proposed algorithm is based on the real-coded expended compact genetic algorithm (rECGA) and evolutionary strategy (ES), which combines advantages of linkage learning from genetic algorithm (GA) and exploration ability from ES for robust global optimizations. Due to the specific design of the proposed algorithm for matching network synthesis, the possibility of immature convergence is reduced and the optimum matching network can be found rapidly. Besides, the proposed algorithm can simultaneously find many sub-optimal circuits with different topology, which makes the design flexible in choosing the desired circuit architecture. In order to validate the proposed algorithm, several experiments have been performed and analyzed, and the results show that our algorithm outperforms the previously published works. Two monolithic microwave integrated circuits (MMICs) are also implemented using our algorithm. The first one is a 110-180 GHz broadband amplifier in 65-nm CMOS process, which is the first CMOS amplifier covering the full D-band. The second circuit is a two-stage Ka-band power amplifier in 0.1-μm GaAs pHEMT process, which performs broadband response of gain, return loss, output power and high power-added efficiency (PAE).