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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
dc.contributor.author | Bo-Jyun Chen | en |
dc.contributor.author | 陳柏均 | zh_TW |
dc.date.accessioned | 2021-06-16T08:44:42Z | - |
dc.date.available | 2020-07-17 | |
dc.date.copyright | 2020-07-17 | |
dc.date.issued | 2020 | |
dc.date.submitted | 2020-07-08 | |
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[2] Y.-K. Lin and J. G. Hwu, “Role of lateral diffusion current in perimeterdependent current of MOS(p) tunneling temperature sensors,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3562–3565, Oct. 2014. [3] Chen, Tzu-Yu Hwu, Jenn-Gwo. (2012). Two states phenomenon in the current behavior of metal-oxide-semiconductor capacitor structure with ultra-thin SiO2. Applied Physics Letters. 101. 10.1063/1.4746284. [4] Kao, W.-C Chen, J.-Y Hwu, J.-G. (2016). Two States Phenomenon Induced By Neighboring Device Coupling Effect in MIS(p) Tunnel Current. ECS Transactions. 72. 223-230. 10.1149/07202.0223ecst. [5] C. Liao, W. Kao and J. Hwu, 'Energy-Saving Write/Read Operation of Memory Cell by Using Separated Storage Device and Remote Reading With an MIS Tunnel Diode Sensor,' in IEEE Journal of the Electron Devices Society, vol. 4, no. 6, pp. 424-429, Nov. 2016. doi: 10.1109/JEDS.2016.2591956. [6] S. K. Ghandhi, VLSI Fabrication Principles, 2nd ed., Wiley-Interscience, pp. 487-495, 1994 [7] Shishiyanu, S.T Oleg, Lupan Shishiyanu, T.S Şontea, V. Railean, S.. (2004). Properties of SiO2 thin films prepared by anodic oxidation under UV illumination and rapid photothermal processing. Electrochimica Acta. 49. 4433-4438. 10.1016/j.electacta.2004.04.034. [8] Parkhutik, Vitali. (2000). New effects in the kinetics of the electrochemical oxidation of silicon. Electrochimica Acta - ELECTROCHIM ACTA. 45. 3249-3254. 10.1016/S0013-4686(00)00411-4. [9] Ting, Chieh-Chih Shih, Yen-Hao Hwu, Jenn-Gwo. (2002). Ultralow leakage characteristics of ultrathin gate oxides (~3 nm) prepared by anodization followed by high-temperature annealing. Electron Devices, IEEE Transactions on. 49. 179 - 181. 10.1109/16.974766. [10] Jeng, Ming-Jer Hwu, Jenn-Gwo. (1997). Thin-gate oxides prepared by pure water anodization followed by rapid thermal densification. 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Hwu, 'Subthreshold Swing Reduction by Double Exponential Control Mechanism in an MOS Gated-MIS Tunnel Transistor,' in IEEE Transactions on Electron Devices, vol. 62, no. 6, pp. 2061-2065, June 2015. doi: 10.1109/TED.2015.2424245. [17] Y. Lin and J. Hwu, 'Photosensing by Edge Schottky Barrier Height Modulation Induced by Lateral Diffusion Current in MOS(p) Photodiode,' in IEEE Transactions on Electron Devices, vol. 61, no. 9, pp. 3217-3222, Sept. 2014. doi: 10.1109/TED.2014.2334704. [18] Cheng, Jen-Yuan Huang, Chiao-Ti Hwu, Jenn-Gwo. (2009). Comprehensive study on the deep depletion capacitance-voltage behavior for metal-oxide-semiconductor capacitor with ultrathin oxides. Journal of Applied Physics. 106. 074507 - 074507. 10.1063/1.3226853. [19] Liao, C.-S Hwu, J.-G. (2016). Current Coupling Effect in MIS Tunnel Diode with Coupled Open-Gated MIS Structure. ECS Transactions. 75. 77-86. 10.1149/07505.0077ecst. [20] G. Bersuker et al., 'Breakdown in the metal/high-k gate stack: Identifying the “weak link” in the multilayer dielectric,' 2008 IEEE International Electron Devices Meeting, San Francisco, CA, 2008, pp. 1-4. [21] Butcher, J.B.. (1984). MOS Physics and Technology, Nicollian, Brews. Pub. Wiley (1982), £70.80. Microelectronics Journal. 15. 71. 10.1016/s0026-2692(84)80036-1. [22] Hanbin Yoon et al., “Efficient Data Mapping and Buffering Techniques for Multilevel Cell Phase-Change Memories.” ACM Trans. Archit. Code Optim. 11, 4, Article 40 (December 2014), 25 pages. doi: 10.1145/2669365. [23] Stathopoulos, S., Khiat, A., Trapatseli, M. et al., “Multibit memory operation of metal-oxide bi-layer memristors.” Sci Rep 7, 17532 (2017) doi:10.1038/s41598-017-17785-1. [24] Baudry, L., Lukyanchuk, I. Vinokur, V, “Ferroelectric symmetry-protected multibit memory cell.” Sci Rep 7, 42196 (2017) doi:10.1038/srep42196. [25] J. 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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/59016 | - |
dc.description.abstract | 本篇論文經由電流、電容及電荷儲存特性深入地探討邊緣經蝕刻之氧化鋁介電質對於金氧半穿隧二極體的影響。其行為相對於不具有蝕刻邊緣的元件呈現明顯差異,主要導因為經由蝕刻製程,有陷阱在邊緣形成。氧化鋁層的厚度也是影響電荷儲存特性的重要因素。在一個週期的正負施加偏壓後,可以觀察到相反的平帶電壓平移,說明在不同的氧化鋁厚度中,特性由相異的注入機制主導。對於一擁有較薄氧化鋁的金氧半元件,由電極注入的電子主導電荷儲存特性。而在擁有較厚氧化鋁的元件中,則是由基板注入的電洞主導。氧化鋁接著被應用於同心圓電荷耦合穿隧二極體閘極的介電層。若電子被儲存於介電層中,中心的二極體會感應到較小的電流。相較於僅有二氧化矽介電層的電荷耦合穿隧二體極,氧化鋁使元件擁有更大的電流窗口以及較佳的保留特性。具備不同厚度氧化鋁厚度的耦合元件展現相異的耐久特性,而這個結果和在單一金氧半元件上的實驗是一致的。基於穩定的電流窗以及較長的電荷保留性,我們建議較薄的氧化鋁介電層較適合作為記憶體應用。由於儲存在邊緣的電荷數量可以藉由不同的偏壓條件調控,多位階的特性被進一步地展示,同時以可調變阻抗方式呈現似類比行為實驗,研究過程詳細地探討施加偏壓大小以及持續時間的影響。實驗中金氧半穿隧二極體展現的多位階特徵及似類比行為展現了可做為記憶體和人工神經網路中突觸元件的潛力。儘管此元件體積在現階段是大的,其邊緣感應機制使得尺寸微縮是可行的。微縮的概念同時藉由二維TCAD模擬輔助說明。在內文中,也提出了對未來研究的數個建議以提升此元件在各方面的表現。 | zh_TW |
dc.description.abstract | In this thesis, the effects of an edge-etched Al2O3 dielectric in a metal-insulator-semiconductor (MIS) tunnel diode are thoroughly investigated by I-V, C-V and charge storage characteristics. The behaviors are obviously different from the device without an etched edge. It is suggested that traps are formed at the edge because of the etching process. The thickness of the Al2O3 layer is also an important factor affecting the charge storage characteristic. Opposite flat-band voltage shifts are observed in a cycle of positive and negative voltage stress indicating distinct injection mechanism in various thickness. Electron injection from electrode dominates in MIS with thinner Al2O3 while hole injection from substrate dominates in device with thicker Al2O3. The Al2O3 is then applied as an additional layer of gate dielectric in a concentric charge-coupled MIS TD. If electrons are trapped in the surrounded gate, the center TD will sense a minor current. The MIS TD coupled with Al2O3 shows larger current window and better retention characteristic compared to the one with SiO2 dielectric only. Devices coupled with various thickness of Al2O3 exhibit different endurance characteristics and the results are consistent with the experiment performed on single MIS. We suggest a thinner Al2O3 dielectric is suitable for memory application due to its stable current window and longer retention. Since the quantities of stored charges stored at the edge can be modulated by various stress conditions, multilevel characteristic is further demonstrated. Analog-like behavior expressed by tunable conductance is also performed and the effects of stress magnitude and duration are discussed in detail. With multilevel characteristic and analog-like behavior, the charge-coupled MIS TD has potential for applications as memory cell and synaptic device in artificial network. Although the device is large in current status, downscaling is feasible due to the edge-sensing mechanism and the concept is illustrated by 2D TCAD simulation. Several suggestions are also mentioned for future works to obtain better performance in all aspects. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:44:42Z (GMT). No. of bitstreams: 1 U0001-0807202016175600.pdf: 3482734 bytes, checksum: d0d0a5bf7ab0c17d59eab19d9ccc4f28 (MD5) Previous issue date: 2020 | en |
dc.description.tableofcontents | 摘要………………………………………………………………………I Abstract………………………………………………………………II Contents………...……………………………………………………………III Figure Captions….….…….……………………………………………………V Chapter 1 Introduction……..….………………………………………………1 1-1 Motivation……………………………………………………………………………1 1-2 Dielectric Growth Mechanism………………………………………………………3 1-2-1 Silicon Oxide by Anodization System………………………………………3 1-2-2 Aluminum Oxide by Deposition and Oxidation……………………………………4 1-3 Oxide Thickness Determination by Electrical Characteristic…………………………5 1-4 Electrical Characteristics and the Schottky Barrier Height Modulation of MIS(p) Tunnel Diodes……………………………………………………………………6 1-5 Memory Characteristics of Charge-Coupled MIS(p) Tunnel Diodes……………8 1-6 Summary………………………………………………………………………..10 Chapter 2 Effects and Modeling of Additional Edge-etched Al2O3 Dielectric Layer in MIS(p) TD…………………………………………17 2-1 Introduction……………………………………………………………………………17 2-2 Experimental……………………………………………………………………18 2-3 Results and Discussion……………………………………………………………19 2-3-1 Electrical Characteristics of Distinct Structures……………………………19 2-3-2 Modeling of the Etched Al2O3 Edge………………………………………21 2-3-3 Relation between Al2O3 Structure and Charge Storage Characteristic…22 2-4 Summary…………………………………………………………………………24 Chapter 3 Advantages of Edge-Etched Al2O3 as Gate Dielectric in Charge-Coupled MIS TD and Its Multilevel Characteristic Demonstration………………………………………………………………33 3-1 Introduction…………………………………………………………………………33 3-2 Experimental…………………………………………………………………………34 3-3 Results and Discussion……………………………………………………………35 3-3-1 Charge-Coupled MIS TD with and without Edge-Etched Al2O3………………35 3-3-2 Relation between Al2O3 Thickness and Memory Characteristic………38 3-3-3 Relation between SiO2 Thickness and Memory Characteristic…………39 3-3-4 Multilevel Characteristic Demonstration………………………………41 3-3-5 Analog-Like Behavior Performed by Tunable Conductance………………43 3-4 Summary………………………………………………………………………45 Chapter 4 Conclusion and Future Work…………………………60 4-1 Conclusions……………………………………………………………………………60 4-2 Suggestions for Future Work and Its Feasibility…………………………………61 References……………………………………………………………69 | |
dc.language.iso | en | |
dc.title | 邊緣蝕刻氧化鋁介電層在感應耦合金氧半穿隧二極體多位階電荷儲存之研究 | zh_TW |
dc.title | Study of Edge-Etched Al2O3 Dielectric as Multi-Level Charge Storage Region in an Edge-Sensing Coupled MIS(p) TD | en |
dc.type | Thesis | |
dc.date.schoolyear | 108-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 林致廷(Chih-Ting Lin),張子璿(Tzu-Hsuan Chang) | |
dc.subject.keyword | 穿隧二極體,耦合, | zh_TW |
dc.subject.keyword | MIS TD,Coupling,Multilevel, | en |
dc.relation.page | 73 | |
dc.identifier.doi | 10.6342/NTU202001387 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2020-07-09 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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