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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58852完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 陳中平 | |
| dc.contributor.author | Bor-Tsang Hwang | en |
| dc.contributor.author | 黃柏蒼 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:34:46Z | - |
| dc.date.available | 2023-11-27 | |
| dc.date.copyright | 2014-01-27 | |
| dc.date.issued | 2013 | |
| dc.date.submitted | 2013-11-27 | |
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| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58852 | - |
| dc.description.abstract | 隨著製程的演進，信號擺幅以及供應電壓持續的降低。因此，今日的電壓調節器必需在負載變動時能做出快速的反應並且維持穩定的輸出電壓。傳統的電流模式降壓型轉換器，由於頻寬上的限制無法擁有快速的暫態響應。在本論文中我們提出兩個新的架構來改善這個問題。
在切換式轉換器中，由於電感的限制電流無法立即改變，因此有文獻提出使用輸出電流泵的方式，在暫態時來補償電感電流與輸出電流的落差。然而這個架構無法直接適用於電流模式降壓型轉換器上。在第一顆晶片中，我們針對這個架構進行修正，提出適應性雙電流泵的方式。由於輸出電流泵會影響到原本迴路的運作，我們使用另一電流泵去彌補這個方式對於補償電路上的影響。這個架構被實現於TSMC 0.35μm CMOS製程。量測結果顯示暫態響應的回復時間約為2.8~4 μs。相較於傳統架構而言，回復時間被減少了約75%。另外，在輸出電流介於120~600 mA間，轉換效率皆大於82 %；與傳統架構相比，這個架構所造成的效率衰減皆小於0.3%。 在第二顆晶片中，我們使用動態調整補償電路電壓的方式。在電流模式控制中，補償電容上的電壓需要隨不同負載而有所變動。因此，藉由將電感電流的資訊加到補償電路的輸出上，使得當不同負載時補償電容所需的電壓變動量較傳統架構減少，藉此來達到較快的反應速度。這個架構被實現於TSMC 0.25μm CMOS製程。佈局後模擬顯示其暫態響應的回復時間約為3~6 μs。而實現這個架構所需要增加的面積約為57.5k μm2，遠較前一個架構所需要增加的面積小(333k μm2)。另外，在輸出電流介於100~500 mA間，轉換效率皆大於90%；與傳統架構相比，這個架構所造成的效率衰減皆小於0.4%。 | zh_TW |
| dc.description.abstract | With the evolution of the process, the supply voltage and the signal level decreases. Therefore, fast load transient response to keep output voltage stable and clean becomes very critical for voltage regulators nowadays. Traditional current mode buck converter cannot attain fast transient response due to bandwidth limitations. In this thesis, we propose two new architectures to improve this problem.
The output current slew rate of switching converters is restricted by the inductor. Therefore, the additional current pump is proposed in the literature to provide the insufficient current between the inductor and the output load when loading is changed suddenly. However, this architecture cannot apply to the current mode buck converters directly. In the first chip, we modify this architecture and adopt the adaptive dual current pump technique. Since the output current pump will affect the operation of the original loop, the other current pump is added to make up its impact on the compensation circuit. This technique is implemented with TSMC 0.35μm CMOS process. Measurement results show the recovery time is within 2.8~4 μs. Compared with conventional design, the performance of recovery time is reduced by about 75%. In addition, power conversion efficiency is larger than 82% with load current between 120 mA and 600 mA in proposed architecture. Efficiency degradation is less than 0.3% compared with conventional architecture. In the second chip, we use the dynamic voltage adjustment of the compensation circuit technique. In current mode control, the voltage of the compensation capacitor needs to be changed according to different load conditions. By adding the inductor current signal to the output of the compensation circuit, the voltage difference of the compensation capacitor at different loads can be reduced. As a result, faster transient response is obtained. This technique is implemented with TSMC 0.25μm CMOS process. Post-layout simulation results show the recovery time is within 3~6 μs. The additional area for implementing this technique is 57.5k μm2, which is much smaller than the previous technique (333k μm2). In addition, power conversion efficiency is larger than 90 % with load current between 100 mA and 500 mA in proposed architecture. Efficiency degradation is less than 0.4% compared with conventional architecture. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:34:46Z (GMT). No. of bitstreams: 1 ntu-102-R99943138-1.pdf: 5540772 bytes, checksum: 4ddc3f3bd0be8689115cb8d590127fd4 (MD5) Previous issue date: 2013 | en |
| dc.description.tableofcontents | 誌謝 i
摘要 iii Abstract v Contents vii List of Figures xii List of Tables xx Chapter 1 Introduction 1 1.1 Background of Regulators 1 1.2 Classification of Voltage Regulators 2 1.2.1 Linear Regulators 2 1.2.2 Switching Capacitor Circuits 4 1.2.3 Switching Regulators 6 1.3 Design Motivation 9 1.4 Specification 11 1.5 Thesis Organization 12 Chapter 2 Fundamentals of DC-DC Buck Converter 13 2.1 General Specifications 13 2.1.1 Efficiency 13 2.1.2 Regulation 16 2.1.3 Transient Response 17 2.2 Operation of DC-DC Buck Converter 20 2.3 Ripple-Based and PWM Control Mechanism 27 2.4 Voltage-Mode and Current-Mode Buck Converter 30 2.4.1 Voltage Mode Buck Converter 31 2.4.2 Current Mode Buck Converter 33 Chapter 3 Adaptive Dual Current Pump Technique for Current Mode Buck Converters…… 37 3.1 Prior Works 37 3.1.1 Current Pump Technique 37 3.1.2 Dual Mode Control Technique 39 3.1.3 Gm-Enhancement Technique 41 3.1.4 Adaptive Pole-Zero Position Technique 42 3.2 Proposed Architecture 44 3.2.1 Analysis of Prior Works 44 3.2.2 Proposed Architecture 49 3.2.3 Behavior Model Simulation 51 3.3 Circuit Level Implementation 54 3.3.1 Flash ADC 54 3.3.2 Comparator with Preamplifier 55 3.3.3 Current Pump 58 3.3.4 Transconductance Amplifier 59 3.3.5 Comparator 61 3.3.6 Oscillator and Ramp Generator 64 3.3.7 Current Sensor 66 3.3.8 V-I Converter 68 3.3.9 Buffer and Dead-Time Control 70 3.3.10 Soft-Start 72 3.4 Layout & Post-Layout Simulation 73 3.4.1 Layout 73 3.4.2 Post-Layout Simulation Results 74 3.5 Measurement 79 3.5.1 Chip Photo 79 3.5.2 Measurement Setup 79 3.5.3 Measurement Results 80 3.5.3 Comparison Table 86 3.6 Issues of this Chip 86 Chapter 4 Dynamic Voltage Adjustment of the Compensation Circuit for Current Mode Buck Converter 88 4.1 Proposed Architecture 88 4.1.1 Analysis of the Proposed Architecture 88 4.1.2 Stability Consideration 92 4.1.3 Behavior Model Simulation 95 4.2 Circuit Level Implementation 96 4.2.1 Modification of the Comparator with Reset Function 97 4.2.2 Modification of the Current Sensor with Negative Inductor Current Sensing 102 4.2.3 Sample and Delay Circuit 106 4.2.4 Auxiliary Gm Circuit 108 4.2.5 Decision Circuit 111 4.2.6 Dynamic Voltage Adjustment Circuit 113 4.2.7 Adaptive Resistance Circuit 114 4.3 Layout & Post-layout Simulation 117 4.3.1 Layout 117 4.3.2 Post-Layout Simulation Results 117 4.3.3 Compared with Conventional Architecture 121 4.3.4 Comparison Table 123 Chapter 5 Conclusion and Future Works 124 5.1 Conclusion 124 5.2 Future Works 125 REFERENCES 126 | |
| dc.language.iso | en | |
| dc.title | 具適應性負載暫態響應提升技術的電流模式降壓型轉換器之設計與實現 | zh_TW |
| dc.title | Design and Implementation of the Current Mode Buck Converter with Adaptive Load Transient Enhancement Techniques | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 陳科宏,陳耀銘,林宗賢 | |
| dc.subject.keyword | 降壓型轉換器,電流模式控制,暫態響應,電流泵,補償電路, | zh_TW |
| dc.subject.keyword | buck converter,current mode control,transient response,current pump,compensation circuit, | en |
| dc.relation.page | 132 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2013-11-27 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| 顯示於系所單位： | 電子工程學研究所 | |
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