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http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58755Full metadata record
| ???org.dspace.app.webui.jsptag.ItemTag.dcfield??? | Value | Language |
|---|---|---|
| dc.contributor.advisor | 陳信樹(Hsin-Shu Chen) | |
| dc.contributor.author | Yao-Sheng Hu | en |
| dc.contributor.author | 胡耀升 | zh_TW |
| dc.date.accessioned | 2021-06-16T08:29:16Z | - |
| dc.date.available | 2019-03-18 | |
| dc.date.copyright | 2014-03-18 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-01-08 | |
| dc.identifier.citation | [1] H. W. Chen, “Energy Efficient Nyquist Rate Analog to Digital Converter,” Graduate Institute of Electronics Engineering College of Electrical Engineering & Computer Science National Taiwan University doctoral dissertation, Chapter 7, pp. 108-134, March 2012.
[2] B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGRAW-HILL INTERNATIONAL EDITION, August 2000. [3] B. Razavi, “Principles of Data Conversion System Design,” Wiley-IEEE Press, November 1994. [4] R. E. J. van de Grift, et al., “An 8-bit video ADC incorporating folding and interpolation techniques,” IEEE J. Solid-State Circuits, vol. SC-22, no. 6, pp. 944-953, December 1987. [5] S. Chang, et al., “BioBolt: A minimally-invasive neural interface for wireless epidural recording by intra-skin communication,” IEEE Symp. VLSI Circuits, pp. 146-147, June 2011. [6] C. C. Liu, et al., “A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS,” IEEE Symp. VLSI Circuits, pp. 241-242, June 2010. [7] C. Y. Liou, et al., “A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS” IEEE ISSCC Dig. Tech. Papers, pp. 280-281, February 2013. [8] P. Harpe, et al., “A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction,” IEEE ISSCC Dig. Tech. Papers, pp. 270-271, February 2013. [9] H. Y. Tai, et al., “A 0.85fJ/conversion-step 10-bit 200kS/s subranging SAR ADC in 40nm CMOS” IEEE ISSCC Dig. Tech. Papers, Accepted Papers, February 2013. [10] H. Y. Tai, et al., “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS,” IEEE Symp. VLSI Circuits, pp. 92-93, June 2012. [11] M. Alioto, “Ultra-low power VLSI circuit design demystified and explained: A tutorial,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 59, no. 1, pp. 3-29, January 2012. [12] G. Moritz, et al., “Optimization of a Voltage Sense Amplifier operating in Ultra Wide Voltage Range with Back Bias Design Techniques in 28nm UTBB FD-SOI Technology,” IEEE ICICDT 2013 Session C - Low Power, pp. 53-56, May 2013. [13] G. Promitzer, “12-bit low-power differential switched capacitor noncalibrating successive approximation ADC with 1 MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, July 2001. [14] H. Y. Tai, et al., “A 0.004 mm2 single channel 6b 1.25GS/s SAR ADC,” IEEE ASSCC Dig. Tech. Papers, pp. 278-280, November 2013. [15] B. P. Ginsburg, et al., “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 184-187, June 2005. [16] M. V. Elzakker, et al., “A 10-bit charge redistribution ADC consuming 1.9uW at 1 MS/s,” IEEE J. Solid-State Circuits, vol. 45, no. 5, pp. 1007-1015, May 2010. [17] C. C. Liu, et al., “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation,” IEEE ISSCC Dig. Tech. Papers, pp. 386-387, February 2010. [18] F. Kuttner, “A 1.2 V 10b 20 MSample/s nonbinary successive approximation ADC in 0.13 um CMOS,” IEEE ISSCC Dig. Tech. Papers, pp. 176-177, February 2002. [19] P. Harpe, et al., “A 26uW 8 bit 10 MS/s asynchronous SAR ADC for low energy radios,” IEEE J. Solid-State Circuits, vol. 46, no. 7, pp. 1585-1595, July 2011. [20] D. Stepanovic, et al., “A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS,” IEEE Symp. VLSI Circuits, pp. 84-85, June 2012. [21] S. J. Chang, et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010. [22] V. Hariprasath, et al., “Merged capacitor switching based SAR ADC with highest switching energy-efficiency,” IET Electronics Letters, vol. 46, no. 9, pp. 620-621, April 2010. [23] C. H. Kuo, et al., “A high energy-efficiency SAR ADC based on partial floating capacitor switching technique,” IEEE ESSCIRC, pp. 475–478, September 2011. [24] P. Nuzzo, et al., “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 7, pp. 1441-1454, July 2008. [25] B. Wicht, et al., “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148-1158, July 2004. [26] Sedra and Smith, “Microelectronic Circuit,” International Student Edition 5ed, 2004. [27] E. Janssen1, et al., “An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS” IEEE ISSCC Dig. Tech. Papers, pp. 464-465, February 2013. [28] B. Murmann, 'ADC Performance Survey 1997-2013,' [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58755 | - |
| dc.description.abstract | 類比數位轉換器在電子系統中扮演極重要的角色，它是自然界類比信號與數位信號中間的橋梁。近年來隨著低功率的電子產品的需求越來越高，特別是應用在無線通訊、感應器與生醫系統中，所以如何降低類比數位轉換器的耗電以及如何能在低電壓下類比數位轉換器還能正常的運作儼然成為一個非常熱門的題目。在各種不同的架構中，連續漸進式式類比數位轉換器不需要放大器且內部架構大部分都是數位電路，因此可以達到在低電壓與低功率下運作的要求。
本論文主要提出一個新的偵測與迴避演算法搭配一個新的同步切換省電技巧，運用在連續漸進式類比數位轉換器當中，不需額外的校正，就可以達到低電壓與低功率消耗。此演算法驗證於台積電低壓40奈米製程10位元連續漸進式類比數位轉換器，工作電壓為0.45伏特，單通道轉換速度為每秒二十萬次，功耗只有84奈瓦，獲得8.95的有效位元，並將FoM下降到只剩下0.85 fJ/conversion-step，因為沒有額外的校正電路，主電路所占面積只有0.0065平方毫米。在奈奎斯特頻率下，SNDR、SFDR、SNR與THD等動態的表現分別為55.63dB、76.25dB、55.75dB與71.3dB。運用細心與對稱的電路佈局搭配1.5fF的小單位電容，將靜態特性達到+0.29/-0.44 LSB的差動非線性(DNL)、+0.45/-0.29 LSB的積分非線性(INL)表現。 | zh_TW |
| dc.description.abstract | Today analog to digital converter (ADC) plays an important role in electronic systems. It is a bridge between nature analog environment and digital world. Recently requirement of low power application grows gradually, especially in wireless communication, sensor network and biomedical system. As the result, how to decrease the power dissipation of ADC and how to make ADC operate at ultra low voltage system become big issues. In different types of ADC, successive approximation register (SAR) ADC does not have op-amplifier and most blocks are only digital circuits, so SAR ADC can achieve the low power and low voltage specification.
The thesis proposes the new detect-and-skip algorithm combined with aligned switching technique which is used in SAR ADC. This SAR ADC does not need additional calibration to achieve low power dissipation and low voltage operation. The algorithm and technique are verified by TSMC 1P6M3X1Z1U Low Power CMOS process. This work operates at in 0.45V supply voltage. Its power dissipation is only 84nW and gets 8.95 bit ENOB performance. As the result, the performance is decreased to . Without additional calibration circuit, the core circuit area is only 0.0065mm2. At Nyquist rate frequency, the dynamic performance parameters like SNDR, SFDR, SNR and THD are 55.63dB, 76.25dB, 55.75dB and 71.3dB respectively. By careful and symmetric layout, the static performance parameters of differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.29/-0.44 LSB and +0.45/-0.29 LSB respectively. The value of unit capacitor is only 1.5fF. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T08:29:16Z (GMT). No. of bitstreams: 1 ntu-103-R01943022-1.pdf: 6497669 bytes, checksum: 37b32a27e88818ef7554dc56e9649d3a (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | Chapter 1 INTRODUCTION
________________________________________ 1.1 Motivation 1 1.2 Thesis Organization 1 Chapter 2 FUNDAMENTALS OF ANALOG TO DIGITAL CONVERTER ________________________________________ 2.1 Introduction 3 2.2 Performance 3 2.2.1 Offset and Gain Error 3 2.2.2 Differential and Integral Nonlinearity (DNL, and INL) 4 2.2.3 Signal-to-Noise Ration (SNR) 5 2.2.4 Total Harmonic Distortion (THD) 6 2.2.5 Spurious-Free Dynamic Range (SFDR) 7 2.2.6 Signal-to-Noise and Distortion Ratio (SNDR) 7 2.2.7 Effective Number of Bits (ENOB) 7 2.2.8 Figure of Merit (FoM) 7 2.3 Architecture of Analog to Digital Converter 8 2.3.1 Flash ADC Architecture 9 2.3.2 Two-Step and Subranging Architecture 10 2.3.3 Pipeline Architecture 11 2.3.4 Successive-Approximation Register Architecture 13 Chapter 3 ENERGY-EFFICIENT CONCEPT ________________________________________ 3.1 Introduction 15 3.2 Energy-Efficient Concept 17 3.2.1 Advanced Technology Trend 17 3.2.2 Ultra Low Voltage 18 3.2.3 High Threshold Voltage 19 3.2.4 Asynchronous Architecture 20 3.2.5 Duty Cycle 21 3.2.6 Charge Redistribution DAC 22 3.2.6.1 Decrease Unit Capacitor Size 22 3.2.6.2 Improve Capacitor Switching Method 23 3.3 Summary 25 Chapter 4 PROPOSED ARCHITECTURE AND BLOCK IMPLEMENTATION ________________________________________ 4.1 Introduction 26 4.2 Architecture 27 4.3 Proposed Capacitor Switching Algorithm and Technique 28 4.3.1 Detect-and-Skip Algorithm 28 4.3.2 Aligned Switching Technique 31 4.3.3 Split-Monotonic Switching Method 33 4.3.4 Summary 35 4.4 Error Correction 36 4.5 Block Implementation 37 4.5.1 Comparator 37 4.5.1.1 Comparator Time-Domain Transient Waves 38 4.5.1.2 Noise Design Consideration 39 4.5.1.3 Offset Design Consideration 41 4.5.1.4 Comparator Design Summary 42 4.5.2 Capacitor Array 43 4.5.3 Bootstrap Circuit 46 4.6 Overall ADC Simulation Results 50 Chapter 5 CHIP SETUP AND MEASUREMENT RESULT ________________________________________ 5.1 Introduction 53 5.2 Chip Setup 53 5.2.1 Chip Layout Introduction 53 5.2.2 Measurement Instrument 54 5.2.3 PCB design 56 5.3 Measurement Result 58 5.3.1 Static Performance 59 5.3.2 Dynamic Performance 60 5.3.3 Power Dissipation 61 5.4 Summary 62 Chapter 6 CONCLUSION ________________________________________ 6.1 Conclusion 64 REFERENCE ________________________________________ | |
| dc.language.iso | en | |
| dc.subject | 小面積 | zh_TW |
| dc.subject | 類比/數位轉換 | zh_TW |
| dc.subject | 連續漸進式 | zh_TW |
| dc.subject | 低功率 | zh_TW |
| dc.subject | 低電壓 | zh_TW |
| dc.subject | ADC | en |
| dc.subject | SAR ADC | en |
| dc.subject | low power | en |
| dc.subject | low voltage | en |
| dc.subject | small area | en |
| dc.title | 一個低功率的連續漸進式數位轉換器 | zh_TW |
| dc.title | A Low Power Successive-Approximation Register ADC | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-1 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),蔡宗亨(Tsung-Heng Tsai) | |
| dc.subject.keyword | 類比/數位轉換,連續漸進式,低功率,低電壓,小面積, | zh_TW |
| dc.subject.keyword | ADC,SAR ADC,low power,low voltage,small area, | en |
| dc.relation.page | 67 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-01-09 | |
| dc.contributor.author-college | 電機資訊學院 | zh_TW |
| dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
| Appears in Collections: | 電子工程學研究所 | |
Files in This Item:
| File | Size | Format | |
|---|---|---|---|
| ntu-103-1.pdf Restricted Access | 6.35 MB | Adobe PDF |
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