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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 李泰成(Tai-Cheng Lee) | |
dc.contributor.author | Po-Chun Huang | en |
dc.contributor.author | 黃柏鈞 | zh_TW |
dc.date.accessioned | 2021-06-16T08:27:03Z | - |
dc.date.available | 2017-01-27 | |
dc.date.copyright | 2014-01-27 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-01-20 | |
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dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58713 | - |
dc.description.abstract | 本論文呈獻一個操作於2.3億赫茲、500千赫茲頻寬且不具除法器之頻率合成器架構,此架構運用最近被提出的次取樣相位鎖定迴路(sub-sampling phase-locked loop)和再量化三角積分調變器(re-quantized modulator)達成低頻寬內和低頻寬外雜訊,一個數位校正迴路(digital correlation loop)和動態單位相稱(dynamic element matching)被提出當作有效的方法降低非線性以至於此頻率合成器能達到極佳的特性。此頻率合成器利用藉由數位脈波寬度調變器(digital pulse-width modulator)次取樣壓控震盪器(VCO)輸出完成除小數的操作,由於次取樣相位偵測器(sub-sampling phase detector)的鎖定範圍被限制導致可能鎖定在參考頻率的整數倍上,所以一個頻率鎖定迴路(frequency-locked loop)被運用確保正確的操作,一個自動頻率控制(automatic frequency control)被提出去藉由控制電容陣列來拓展操作範圍。這個架構被執行在零點一八微米互補式金氧半製程所實現且其主要面積為0.75平方毫米。在1.8伏特的電源供應下扣除掉壓控震盪器緩衝器(VCO buffer)和輸入參考頻率緩衝器(input reference frequency buffer)總共消耗9.61毫安培,在2.3億赫茲操作下被量測的相位雜訊為-112 dBc/Hz和-134 dBc/Hz在相對於主頻率分別50千赫茲和10兆赫茲。在主頻上被積分的相位雜訊為266毫微微米的抖動量(被積分範圍為10千赫茲到30兆赫茲),質量因數(figure-of-merit)為-239.1dB在被提出的不具除法器和低雜訊除小數頻率合成器。 | zh_TW |
dc.description.abstract | This thesis presents a 2.3 GHz, 500 kHz bandwidth divider-less frequency synthesizer architecture that leverages a recently invented sub-sampling phase-locked loop (SSPLL) and a re-quantized modulator to achieve lower in-band and out-of-band noise. A digital correlation loop (DCL) and dynamic element matching (DEM) are proposed as an efficient method to reduce the non-linearity so that the synthesizer can achieve excellent performance. The synthesizer sub-samples the VCO output by a digital pulse-width modulator (DPWM) to perform fractional-N operation. Because the sub-sampling phase detector (SSPD) has a limited locking range and may lock to any possible integer multiple of reference clock, a frequency-locked loop (FLL) is added to ensure proper operation. The automatic frequency control (AFC) is proposed to extend the operated range of VCO by capacitor array controlled. The prototype is implemented in a 0.18-µm 1P5M CMOS process and its active area occupies 0.75 mm2. Operating under 1.8V, the core parts, excluding the VCO buffer and the input reference frequency buffer, dissipate 9.61mA. Measured phase noise at 2.3GHz achieves -112dBc/Hz and -134dBc/Hz at 50 kHz and 10 MHz, respectively. Integrated phase noise at this carrier frequency yields 266 fs of jitter (measured from 10 kHz to 30 MHz). The figure-of-merit is -239.1dB on the proposed divider-less low-noise fractional-N synthesizer. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:27:03Z (GMT). No. of bitstreams: 1 ntu-103-R00943030-1.pdf: 18326720 bytes, checksum: a82e0c13ca047961aa848e52d26ac725 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 摘要 i
Abstract ii Contents iii List of Figures vii List of Tables xi Chapter 1 Introduction 13 1.1 Motivation and Research Goals 13 1.2 Thesis Organization 15 Chapter 2 Basic Concepts 17 2.1 Background 17 2.2 Review of the Sub-sampling Phase-Locked Loop 22 2.3 Review of the Multiphase Compensation Method 25 2.4 A Linear Model for Traditional Synthesizer 28 2.5 Summary 30 Chapter 3 Proposed Techniques for Achieving a Low-Noise and Divider-less Fractional-N PLL 31 3.1 Proposed A low-Noise Fractional-N Divider-less Synthesizer 31 3.2 Locking Operation of the Proposed Fractional-N Synthesizer 33 3.3 Challenge of a Low-Noise Synthesizer 34 3.4 Proposed DCL and DEM Techniques 36 3.5 Summary 40 Chapter 4 Circuit Implementation 41 4.1 Subsampling Phase Detector and Charge Pump 41 4.2 Digital Pulse-Width Modulator 43 4.3 Frequency-Locked Loop 45 4.3.1 3-state PFD/CP with Dead Zone 47 4.3.2 Divider 47 4.4 Proposed Automatic Frequency Control 51 4.4.1 Introduction of Previous Work 51 4.4.2 Implementation Details 52 4.4.3 Timing Diagram of the Proposed Synthesizer 55 4.5 VCO 57 4.6 Loop Filter 61 4.7 Summary 62 Chapter 5 Noise Analysis and Behavior Simulation 63 5.1 Linearity Noise Analysis of the Proposed Fractional-N Divider-less Synthesizer 63 5.1.1 PLL Noise Modeling 63 5.1.2 Overall Phase Noise Calculation 66 5.2 Non-linearity Noise Analysis of the Proposed Fractional-N Divider-less Synthesizer 70 5.2.1 Non-linearity Modeling 70 5.2.2 DPWM Non-linearity Noise Calculation 72 5.2.3 SSPD/CP Non-linearity Noise Calculation 77 5.3 Overall Phase Noise Calculation 84 5.4 Behavior Simulation with MATLAB Script 86 5.5 Design Considerations 89 5.5.1 PLL Bandwidth 89 5.5.2 Reference Frequency 91 5.5.3 Phase of the DPWM Circuit 93 5.5.4 Bits of the DAC on the DPWM 94 5.6 Behavior Simulation with Verilog-A Model 95 5.7 Summary 98 Chapter 6 Experimental Results 99 6.1 Print Circuit Board Design 99 6.2 Measurement Environment 100 6.3 Area and Power Dissipation 102 6.4 VCO Gain 103 6.5 Phase Noise and Spurs 106 6.6 Locking Time 112 6.7 Comparison 113 6.8 Summary 113 Chapter 7 Conclusion 115 7.1 Thesis Summary 115 7.2 Future Works 117 Bibliography 119 Biography 125 Publication List 127 | |
dc.language.iso | en | |
dc.title | 以次取樣相位鎖定迴路架構為基礎且不具除法器之低雜訊除小數頻率合成器 | zh_TW |
dc.title | The Design and Analysis of a Low-Noise Divider-less Fractional-N Synthesizer with Sub-Sampling Phase-Locked Loop Architecture | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 劉深淵(Shen-Iuan Liu),陳信樹(Hsin-Shu Chen),鄭國興(Kuo-Hsing Cheng) | |
dc.subject.keyword | 次取樣相位鎖定迴路,不具除法器,低雜訊,除小數頻率合成器,三角積分調變器, | zh_TW |
dc.subject.keyword | sub-sampling phase-locked loop,divider-less,low-noise,fractional-N frequency synthesizers,delta-sigma modulator, | en |
dc.relation.page | 127 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-01-20 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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