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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 黃俊郎 | |
dc.contributor.author | Chung-Hung Lin | en |
dc.contributor.author | 林俊宏 | zh_TW |
dc.date.accessioned | 2021-06-16T08:17:52Z | - |
dc.date.available | 2019-03-18 | |
dc.date.copyright | 2014-03-18 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-02-10 | |
dc.identifier.citation | [1] Bokhari, S.A., “Precision Delay Matching by Trace Length Control in Printed Circuit Boards,” in IEEE CCECE/CCGEI. Canadian Conference, pp. 799-802, 2006.
[2] B. Brown, E.V. Hultine, J.R. Pane, A.D. Firth, C. Jin and B. Yang, “ATE TIMING MEASUREMENT UNIT AND METHOD,” U.S. Patent 6,609,077 B1, August 19, 2003. [3] K. Han, J. Park, J.W. Lee, J. Chung, E. Byun, C.J. Woo, S. Oh and J.A. Abraham, “Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip,” IEEE European Test Symposium, pp. 129-134, May 2009. [4] S.J. Horne and J. Alig, “SYSTEM AND METHOD FOR CALIBRATING SIGNAL PATHS CONNECTING A DEVICE UNDER TEST TO A TEST SYSTEM,” U.S. Patent 7,076,385 B2, July 11, 2006. [5] W.R. Lawrence and D.H. Armstrong, “SYSTEM FOR VERIFYING SIGNAL TIMING ACCURACY ON A DIGITAL TESTING DEVICE.” U.S. Patent 6,192,496 B1, February 20, 2001. [6] R. Mayder, N. Sugihara, A. Tse and R.L. Bailey, “TIMING CALIBRATION AND TINING CALIBRATION VERIFICATION OF ELECTRONIC CIRCUIT TESTERS,” U.S. Patent 6,570,397 B2, May 27, 2003. [7] M. Shimanouchi, “METHOD AND SYSTEM FOR IMPROVED ATE TIMING CALIBRATION AT A DEVICE UNDER TEST,” U.S. Patent 7,120,840 B1, October 10, 2006. [8] G. Torralab, V. Angelov, V. Gonzalez, I. Kisel, V. Lindenstruth, J. Martos, C. Reichling, E. Sanchis, J. Soret and J. Torres, “A VLSI for Deskewing and Fault Tolerance in LVDS Links,” in IEEE-NPSS Real Time Conference, 2005. [9] A. Hu and F. Yuan, “Inter signal Timing Skew Compensation of Parallel Links With Voltage-Mode Incremental Signaling,” IEEE Transactions on Circuits and Systems, vol. 56, pp. 773-783, April 2009. [10] High-Performance DDR2 SDRAM Interface in Virtex-5 Devices. Xilinx, 2010. [11] Creating a Controllable Oscillator Using the Virtex-5 FPGA IODELAY Primitive. Xilinx, 2009. [12] 孫燈亮, 基於TDR規範的阻抗、差分阻抗測試方法及應用. Tektronix EVDC. [13] Test Fundamentals of Digital Semiconductor Testing. Soft Test, 2013. [14] 白安鵬半導體積體電路測試技術部落格: http://ictesting-tom.blogspot.tw/ [15] IC測試經典課程: http://wenku.baidu.com/view/0f75858702d276a200292e48.html [16] K. Mustafa, “Defining Skew, Propagation-Delay, Phase Offset (Phase Error),” Texas Instruments, Dallas, Texas, Application Report, 2001. [17] Stephen H. Hall, Garrett W. Hall and James A. McCall, High-Speed Digital System Design-A Handbook of Interconnect Theory and Design Practices. New York: McGraw-Hill, 1996. [18] S. Brown and J. Rose, “Architecture of FPGAs and CPLDs: A Tutorial,” Department of Electrical and Computer Engineering University of Toronto, 1996. [19] FPGA-表面之下的結構. National Instruments, 2011. [20] 陳宇奕, “基於現場可程式邏輯陣列的低成本次奈秒時序格式產生器,” M.S. thesis, National Taiwan University, 2013. [21] J. Li, Z. Zheng, M. Liu, and S. Wu. “Large dynamic range accurate digitally programmable delay line with 250-ps resolution,” Proceedings of International Conference on Signal Processing (ISCP), 2006. [22] Wishbond System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores. OpenCores, 2010. [23] CDF: http://en.wikipedia.org/wiki/Cumulative_distribution_function [24] Metastability in Altera Devices. Altera, 1998. [25] Least Squares: http://en.wikipedia.org/wiki/Least_squares [26] Wide I/O Single Data Rate (Wide I/O SDR). JESD229, 2011. [27] DE2-70 Development and Education Board User Manual. Terasic Technologies, 2007. [28] DE2-115 Development and Education Board User Manual. Terasic Technologies, 2010. [29] B. Bennetts, “IEEE 1149.1 Boundary-Scan Standard,” Bennetts Associates, 2006. [30] IEEE Standard Test Access Port and Boundary-Scan Architecure. IEEE Std 1149.1-2001, 2001. [31] SN54ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS. Texas Instruments, 1996. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58509 | - |
dc.description.abstract | 隨著製程與封裝技術的進步,使得晶片接腳數量增多,直接影響到半導體自動測試機台 (ATE) 的測試通道數必需增加,測試功能電路板和待測晶片載板的佈線密度勢必提高,使得印刷電路板設計難度提高,成本也跟著大幅提升,且印刷電路板上電路和機構特性上的影響,使得電路會有路徑時間偏差 (Skew) 的問題存在,會造成測試時序錯誤,測試成本提高。
綜合以上問題,需有方法來實現路徑時間偏差的校正功能,讓測試時序的精準度提高,且此方法可使待測晶片載板設計規範放寬,設計難度降低,並降低成本。但目前的校正技術都屬於較高成本或開發時程較長且使用上較不具彈性變動使用,如開發ASIC、專用校正載板或使用外部時序量測儀器。 所以本論文提出以DE2-70 Altera Cyclone II FPGA來實現路徑時序偏差的校正功能,以符合成本較低且使用彈性較高的原則,其主要架構由個人電腦與FPGA共同完成量測的工作,FPGA硬體則由Wishbone匯流排、延遲線 (Delay Line) 電路和控制電路等組成,其中延遲線電路為主要的部份,其解析度會影響到所量測出路徑延遲的準確度,所以選擇LUT-Based的延遲線,其解析度可達15ps,因量測出的數值呈常態機率累積分佈函數,可直接推估得出路徑時序偏差值,再結合圖形化使用者介面的控制和計算,可將校正程序自動化,並在得到補償值後自動補償,驗證後得到的路徑時序偏差可縮小至55ps。 | zh_TW |
dc.description.abstract | With the advance of processing and packaging technology, integrated chip pin counts rise to meet higher demands. To cope with the trend in IC production, the number of test channels on automatic test equipment has to grow. Such changes would directly impact the routing density on both the function board and DUT load board, causing it to become a challenge in board level design and cost management. As a result, the test equipment often suffers path skews due to loading and mechanical effects, resulting in timing error in test sequences.
To reduce the load board design complexity and cost, we need a way to calibrate path skew to improve timing accuracy so that we can relax the PCB design constraints. However, the deskew technique in ATE , such as ASIC, dedicated calibration load board or by external equipment, is very expensive and incurs long development time. The FPGA-based de-skew technique is a promising one due to its low cost and flexibility. The publication proposes a path deskew technique implemented with DE2-70 Altera Cyclone II FPGA and a PC in order to meet the low cost and flexibility. The FPGA system consists of Wishbone bus, Delay Line and counter. The delay line determines the outcome of the experiments, for which its resolution has a directly impact on the accuracy of the measurement. We selected the LUT-Based Delay with 15ps for the deskew system. Because of the measured values were normal cumulative distribution function, path delays can be obtained deriving the cumulative distribution function mean. Experiment processes, including circuit control and data calculation, were done and automated on a self-written program with graphic user interface (GUI). After compensating the skew, we can get the accuracy less than 55ps. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:17:52Z (GMT). No. of bitstreams: 1 ntu-103-R98942108-1.pdf: 3882682 bytes, checksum: 95bbb589438f9da0220d7ae113ceccf0 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | 口試委員會審定書 i
誌謝……………………………………………………………………………………...ii 目錄 v 圖目錄 viii 表目錄 xi Chapter 1 緒論 1 1.1 研究動機與目的 1 1.2 論文架構 3 Chapter 2 相關背景 4 2.1 半導體測試機介紹 4 2.1.1 測試路徑 6 2.2 路徑時序偏差 6 2.2.1 路徑時序偏差的影響與原因 7 2.2.2 傳輸線路延遲時間 9 2.3 路徑時序偏差校正方法 10 2.3.1 使用時序量測儀器 10 2.3.2 設計專用測試載板 (Load Board) 11 2.3.3 開發校正用ASIC 11 2.3.4 使用FPGA實現 12 2.4 FPGA 介紹 13 Chapter 3 基於FPGA的路徑時序校正硬體架構 15 3.1 時序校正硬體架構 16 3.1.1 架構使用原則 17 3.2 建立延遲值表 18 3.2.1 延遲線 18 3.2.2 延遲值排序與建立延遲值表 20 3.3 路徑時序偏差量測 23 3.3.1 時序偏差量測設定 24 3.3.2 待測物需求 26 3.3.3 待測線路時序偏差量測 27 3.3.4 Wishbone Bus 30 3.3.5 取樣結果電路 31 Chapter 4 時序偏差值分析與補償驗證 32 4.1 時序偏差值推算 32 4.2 時序偏差補償與驗證 35 4.2.1 路徑時序偏差補償 35 4.2.2 補償驗證 36 Chapter 5 實驗量測結果 37 5.1 實驗設定與目標 37 5.2 延遲線之延遲值量測配置 37 5.3 實驗架構配置 38 5.3.1 Pesudo DUT實驗架構與設定 39 5.3.2 具有JTAG的待測物實驗架構與設定 42 5.4 Pesudo DUT實驗結果 45 5.5 JTAG DUT實驗結果 48 5.6 圖形使用者介面 51 Chapter 6 結論 52 參考文獻 53 | |
dc.language.iso | zh-TW | |
dc.title | 以現場可程式邏輯陣列實現路徑時序偏差之校正 | zh_TW |
dc.title | Implementation of an FPGA-Based Deskew Technique | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-1 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 洪浩喬,黃炫倫 | |
dc.subject.keyword | 半導體自動測試機台,路徑時間偏差,現場可程式邏輯陣列,延遲線, | zh_TW |
dc.subject.keyword | ATE,TIiming Skew,FPGA,Delay Line, | en |
dc.relation.page | 55 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-02-11 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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