請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58033
完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 胡振國(Jenn-Gwo Hwu) | |
dc.contributor.author | Yen-Kai Lin | en |
dc.contributor.author | 林彥愷 | zh_TW |
dc.date.accessioned | 2021-06-16T08:04:52Z | - |
dc.date.available | 2015-07-08 | |
dc.date.copyright | 2014-07-08 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-06-27 | |
dc.identifier.citation | [1] D. Kahng and M. M. Atalla, “Silicon-silicon Dioxide Field Induced Surface Devices,” in IRE-AIEE Solid-state Device Res. Conf., (Carnegie Inst. of Technol., Pittsburgh, PA), 1960.
[2] International Technology Roadmap for Semiconductors (ITRS): 2012, Semiconductor Industry Association (SIA), Available: www.itrs.net/. [3] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A Self-Aligned Double-Gate MOSFET Scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320–2325, Dec. 2000. [4] S. W. Huang and J. G. Hwu, “Electrical Characterization and Process Control of Cost Effective High-k Aluminum Oxide Gate Dielectrics Prepared by Anodization Followed by Furnace Annealing,” IEEE Trans. Electron Devices, vol. 50, no. 7, pp. 1658–1664, Jul. 2003. [5] C. S. Kuo, J. F. Hsu, S. W. Huang, L. S. Lee, M. J. Tsai, and J. G. Hwu, “High-k Al2O3 Gate Dielectrics Prepared by Oxidation of Aluminum Film in Nitric Acid Followed by High Temperature Annealing,” IEEE Trans. Electron Devices, vol. 51, no. 6, pp. 854–858, Jun. 2004. [6] S. W. Huang and J. G. Hwu, “Lateral Nonuniformity of Effective Oxide Charges in MOS Capacitors with Al2O3 Gate Dielectrics,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1608–1614, Jul. 2006. [7] B. H. Lee, S. C. Song, R. Choi, and P. Kirsch, “Metal Electrode/High-k Dielectric Gate-Stack Technology for Power Management,” IEEE Trans. Electron Device, vol. 55, no. 1, pp. 8–20, Jan. 2008. [8] J. Y. Cheng, H. T. Lu, and J. G. Hwu, “Metal-oxide-semiconductor Tunneling Photodiodes with Enhanced Deep Depletion at Edge by High-k Material,” Appl. Phys. Lett., vol. 96, no. 23, pp. 233506-1–233506-3, June 2010. [9] J. Y. Cheng and J. G. Hwu, “Characterization of Edge Fringing Effect on the C–V Responses From Depletion to Deep Depletion of MOS(p) Capacitors With Ultrathin Oxide and High-κ Dielectric,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 565–572, Mar. 2012. [10] P. L. Hsu, “Edge-Dependent I-V Behavior of MOS Structures with Ultrathin Oxides under Inversion Region,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [11] P. F. Schmidt and W. Michel, “Anodic Formation of Oxide Films on Silicon,” J. Electrochem. Soc., vol. 104, pp. 230, 1957. [12] V. Parkhutik, “New Effects in the Kinetics of the Electrochemical Oxidation of Silicon,” Electrochim. Acta, vol. 45, pp. 3249–3254, 2000. [13] M. Grecea, C. Rotaru, N. Nastase, and G. Craciun, “Physical Properties of SiO2 Thin Films Obtained by Anodic Oxidation,” J. Mol. Struct., pp. 607–610, 1999. [14] D. Gong, C. A. Grimes, O. K. Varghese, W. Hu, R. S. Singh, Z. Chen, and E. C. Dickey, “Titanium Oxide Nanotube Arrays Prepared by Anodic Oxidation,” J. Mater. Res., vol. 16, no. 12, pp. 3331–3334, Dec. 2001. [15] Ch. Comninellis and C. Pulgarin, “Anodic Oxidation of Phenol for Waste Water Treatment,” J. Appl. Electrochem., vol. 21, no. 8, pp. 703–708, Aug. 1991. [16] C. C. Ting, Y. H. Shih, and J. G. Hwu, “Ultralow Leakage Characteristics of Ultrahthin Gate Oxides (~3 nm) Prepared by Anodization Followed by High-Temperature Annealing,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 179–181, 2002. [17] M. J. Jeng, “Application of Anodic Oxidation and Rapid Thermal Treatment on Thin Gate Oxides and Radiatoin-Hardness CMOS sensing circuit,” Ph.D. dissertation, Dept. Elect. Eng., Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 1996. [18] S. K. Ghandhi, VLSI Fabrication Principles, 2nd ed., Wiley-Interscience, pp. 487–495, 1994. [19] E. H. Nicollian and J. R. Brews, MOS Physics and Technology, New York: Wiley, pp. 74, 1981. [20] K. Yang, C. Hu, “MOS Capacitance Measurements for High-Leakage Thin Dielectrics,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1500–1501, July 1999. [21] K. Yang, Y. C. King, and C. Hu, “Quantum Effect in Oxide Thickness Determination from Capacitance Measurement,” in Symp. VLSI Tech. Dig., pp. 77–78, 1999. [22] Berkeley Device Group, Available: www-device.eecs.berkeley.edu/qmcv/. [23] D. J. Griffiths, Introduction to Quantum Mechanics, 2nd ed., Pearson Prentice Hall, pp. 322, 2004. [24] A. Ghetti, C. T. Liu, M. Mastrapasqua, and E. Sangiorgi, “Characterization of Tunneling Current in Ultrathin Gate Oxide,” Solid State Electron., vol. 44, no. 9, pp. 1523–1531, Sep. 2000. [25] T. Y. Chen, “Process Development and Characterization of MOS Capacitor with Ultra-thin Oxide,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2011. [26] N. Yang, W. K. Henson, J. R. Hauser, and J. J. Wortman, “Modeling Study of Ultrathin Gate Oxides Using Direct Tunneling Current and Capacitance–Voltage Measurements in MOS Devices,” IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1464–1471, July 1999. [27] W. C. Lee and C. Hu, “Modeling CMOS Tunneling Currents Through Ultrathin Gate Oxide Due to Conduction- and Valence-Band Electron and Hole Tunneling,” IEEE Trans. Electron Devices, vol. 48, no. 7, pp. 1366–1373, July 2001. [28] F. Li, S. P. Mudanai, Y. Y. Fan, L. F. Register, and S. K. Banerjee, “Physically Based Quantum–Mechanical Compact Model of MOS Devices Substrate-Injected Tunneling Current Through Ultrathin (EOT ~ 1 nm) SiO2 and High-κ Gate Stacks,” IEEE Trans. Electron Devices, vol. 53, no. 5, pp. 1096–1106, May 2006. [29] Y. P. Lin and J. G. Hwu, “Oxide-Thickness-Dependent Suboxide Width and Its Effect on Inversion Tunneling Current,” J. Electrochem. Soc., vol. 151, no. 12, pp. G853–G857, Oct. 2004. [30] C. W. Lee, “A Comprehensive Quantum-Mechanical Model for C-V and I-V Characteristics in Ultrathin MOS Structure and Experimental Verification,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [31] R. Tsu and L. Esaki, “Tunneling in a Finite Superlattice,” Appl. Phys. Lett., vol. 22, no. 11, pp. 562, Mar. 1973. [32] SILVACO Inc., ATLAS User’s Manual, Oct. 2013. [33] R. N. Hall, “Electron-Hole Recombination in Germanium,” Phys. Rev., vol. 87, no.2, pp. 387, July 1952. [34] W. Shockley and W. T. Read, “Statistics of the Recombinations of Holes and Electrons,” Phys. Rev., vol. 87, no. 5, pp. 835–842, Sep. 1952. [35] J. Dziewior and W. Schmid, “Auger Coefficients for Highly doped and Highly Excited Silicon,” Appl. Phys. Lett., vol. 31, no. 5, pp. 346–348, Sep. 1977. [36] J. W. Slotboom and H. C. de Graaff, “Measurements of Bandgap Narrowing in Si Bipolar Transistors,” Solid-State Electron., vol. 19, no. 10, pp. 857–862, Oct. 1976. [37] M. Lundstrom, Fundamentals of Carrier Transport, 2nd ed., Cambridge University Press, 2009. [38] S. Datta, Electronic Transport in Mesoscopic Systems, 1st ed., Cambridge University Press, 1995. [39] S. Altindal, I. Dokme, M. M. Bulbul, N. Yalcin, and T. Serin, “The Role of the Interface Insulator Layer and Interface States on the Current-transport Mechanism of Schottky Diodes in Wide Temperature Range,” Microelectron. Eng., vol. 83, no. 3, pp. 499–505, Mar. 2006. [40] I. Dokme, S. Altindal, “On the Intersecting Behaviour of Experimental Forward Bias Current–voltage (I–V) Characteristics of Al/SiO2/p-Si (MIS) Schottky Diodes at Low Temperatures,” Semicond. Sci. Technol., vol. 21, no. 8, pp. 1053–1058, June. 2006. [41] T. Y. Chen and J. G. Hwu, “Two States Phenomenon in the Current Behavior of Metal-oxide-semiconductor Capacitor Structure With Ultra-thin SiO2,” Appl. Phys. Lett., vol. 101, no. 7, pp. 073506-1–073506-4, Aug. 2012. [42] C. H. Chen, K. C. Chuang, and J. G. Hwu, “Characterization of Inversion Tunneling Current Saturation Behavior for MOS(p) Capacitors With Ultrathin Oxides and High- k Dielectrics,” IEEE Trans. Electron Devices, vol. 56, no. 6, pp. 1262–1268, June 2009. [43] M. Y. Doghish and F. D. Ho, “A Comprehensive Analytical Model for Metal–Insulator–Semiconductor (MIS) Devices,” IEEE Trans. Electron Devices, vol. 39, no. 12, pp. 2771–2780, Dec. 1992. [44] J. Cai and C. T. Sah, “Gate Tunneling Currents in Ultrathin Oxide Metal-oxide-silicon Transistors,” J. Appl. Phys., vol. 89, no. 4, pp. 2272–2285, Feb. 2001. [45] F. Li, S. Mudanai, L. F. Register, and S. K. Banerjee, “A Physically Based Compact Gate C–V Model for Ultrathin (EOT ~ 1 nm and Below) Gate Dielectric MOS Devices,” IEEE Tran. Electron Devices, vol. 52, no. 6, pp. 1148–1158, June 2005. [46] C. H. Choi, J. S. Goo, T. Y. Oh, Z. Yu, R. W. Dutton, A. Bayoumi, M. Cao, P. V. Voorde, D. Vook, and C. H. Diaz, “MOS C–V Characterization of Ultrathin Gate Oxide Thickness (1.3–1.8 nm),” IEEE Electron Device Lett., vol. 20, no. 6, pp. 292–294, June 2009. [47] C. Y. Liu, B. Y. Chen, and T. Y. Tseng, “Deep Depletion Phenomenon of SrTiO3 Gate Dielectric Capacitor,” J. Appl. Phys., vol. 95, no. 10, pp. 5602–5607, May 2004. [48] S. H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, “Quantum-Mechanical Modeling of Electron Tunneling Current from the Inversion Layer of Ultra-Thin-Oxide nMOSFET’s,” IEEE Electron Device Lett., vol. 18, no. 5, pp. 209–211, May 1997. [49] C. S. Tan, K. N. Chen, and S. J. Koester, 3D Integration for VLSI systems, Pan Stanford, 2012. [50] E. E. Aktakka, N. Ghafouri, C. E. Smith, R.L. Peterson, M. M. Hussain, and K. Najafi, “Post-CMOS FinFET Integration of Bismuth Telluride and Antimony Telluride Thin-based Thermoelectric Devices on SOI Substrate,” IEEE Electron Device Lett., vol. 34, no. 10, pp. 1334–1336, Oct. 2013. [51] Y. H. Shih, S. R. Lin, T. M. Wang, and J. G. Hwu, “High Sensitive and Wide Detecting Range MOS Tunneling Temperature Sensors for On-chip Temperature Detection, ” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1514–1521, Sept. 2004. [52] M. Sasaki, M. Ikeda, and K. Asada, “A Temperature Sensor with An Inaccuracy of-1/+0.8 °C Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits,” IEEE T. Semiconduct. M., vol. 21, no. 2, pp. 201–208, May 2008. [53] K. M. Chao, W. C. Lee, W. Liu, X. Jin, P. Su, S. K. H. Fung, J. X. An, B. Yu, and C. Hu, “BSIM4 Gate Leakage Model Including Source-Drain Partition,” in IEDM Tech. Dig., 2000, pp. 815–818. [54] S. M. Sze, Physics of Semiconductor Devices, 3rd ed., John Wiley & Sons, 2007. [55] Y. H. Shih and J. G. Hwu, “An On-chip Temperature Sensor by Utilizing a MOS Tunneling Diode,” IEEE Electron Device Lett., vol. 22, no. 6, pp. 299–301, June 2001. [56] C. H. Lin, B. C. Hsu, M. H. Lee, and C. W. Liu, “A Comprehensive Study of Inversion Current in MOS Tunneling Diode,” IEEE Trans. Electron Devices, vol. 48, no. 9, pp. 2125–2130, Sept. 2001. [57] C. Y. Wang and J. G. Hwu, “Characterization of Stacked Hafnium Oxide (HfO2) / Silicon Dioxide (SiO2) Metal-oxide-semiconductor (MOS) Tunneling Temperature Sensors,” J. Electrochem. Soc., vol.157, vo.10, pp. J324–J328, Oct. 2010. [58] M. du Plessis, H. Aharoni, and L. W. Snyman, “Silicon LEDs Fabricated in Standard VLSI Technology as Components for All Silicon Monolithic Integrated Optoelectronic Systems,” IEEE J. Sel. Top. Quant., vol. 8, no. 6, pp. 1412–1419, Nov. 2002. [59] K. Misiakos, E. Tsoi, E. Halmagean, and S. Kakabakos, “Monolithic Integration of Light Emitting Diodes, Detectors and Optical Fibers on a Silicon Wafers: a CMOS Compatible Optical Sensor,” in IEDM Tech. Dig., Dec. 1998. [60] V. Mohammadi, L.Qi, N. Golshani, C. K. R. Mok, W. B. de Boer, A. Sammak, J. Derakhshandeh, J. van der Cingel, and L. K. Nanver, “VUV/Low-energy Electron Si Photodiodes with Postmetal 400 °C PureB Deposition,” IEEE Electron Device Lett., vol. 34, no. 12, pp. 1545–1547, Dec. 2013. [61] C.W. Liu, W. T. Liu, M. H. Lee, W. S. Kuo, and B. C. Hsu, “A Novel Photodetector Using MOS Tunneling Structures,” IEEE Electron Device Lett., vol. 21, no. 6, pp. 307–309, June 2000. [62] A. El Gamal and H. Eltoukhy, “CMOS Image Sensors,” IEEE Circuits Devices Mag., vol. 21, no. 3, pp. 6–20, June 2005. [63] C. H. Lin and C. W. Liu, “Metal-insulator-semiconductor Photodetectors,” Sensors, vol. 10, no. 10, pp. 8797–8826, Sep. 2010. [64] S. Morita, A. Shinozaki, Y. Morita, K. Nishimura, T. Okazaki, S. Urabe and M. Morita, “Tunneling Current through Ultrathin Silicon Dioxide Films under Light Exposure,” Jpn. J. Appl. Phys., vol. 43, no. 11, pp. 7857–7860, Nov. 2004. [65] B. C. Hsu, S. T. Chang, T. C. Chen, P. S. Kuo, P. S. Chen, Z. Pei, and C. W. Liu, “A High Efficient 820 nm MOS Ge Quantum Dot Photodetector,” IEEE Electron Device Lett., vol. 24, no. 5, pp. 318–320, May 2003. [66] J. Y. Cheng and J. G. Hwu, “Characterization of Edge Fringing Effect on the C-V Responses from Depletion to Deep Depletion of MOS(p) Capacitors with Ultrathin Oxide and High-κ Dielectric,” IEEE Trans. Electron Devices, vol. 59, no. 3, pp. 565–572, Mar. 2012. [67] B. C. Hsu, C. W. Liu, W. T. Liu, and C. H. Lin, “A PMOS Tunneling Photodetector,” IEEE Trans. Electron Devices, vol. 48, no. 8, pp. 1747–1749, Aug. 2001. [68] B. E. Coss, W. Y. Loh, R. M. Wallace, J. Kim, P. Majhi, and R. Jammy, “Near Band Edge Schottky Barrier Height Modulation Using High-κ Dielectric Dipole Tuning Mechanism,” Appl. Phys. Lett., vol. 95, no. 22, pp. 222105-1–222105-3, Dec. 2009. [69] M. Y. Doghish and F. D. Ho, “A Comprehensive Analytical Model for Metal-insulator-semiconductor (MIS) Devices: a Solar Cell Application,” IEEE Trans. Electron Devices, vol. 40, no. 8, pp. 1446–1454, Aug. 1993. [70] P. C. Mathur, J. D. Arora, R. P. Sharma, and P. Saxena, “Dependence of Minority Carrier Diffusion Length on Illumination Level and Temperature in Single Crystal and Polycrystalline Si Solar Cells,” J. Appl. Phys., vol. 52, no. 11, pp. 6949–6953, Nov. 1981. [71] H. W. Lu and J. G. Hwu, “Lateral Nonuniformity of the Tunneling Current of Al/SiO2/p-Si Capacitor in Inversion Region due to Edge Fringing Field Effect,” ECS Trans., vol. 58, no. 7, pp. 339–344, 2013. [72] Y. C. Liao, “Investigation of the Deep Depletion Behavior and Oxide Charge Non-Uniformity Effect in MOS(p) and MOS(n) Devices with Ultra-Thin Oxides,” M.S. Thesis Dept. Elect. Eng. Nat. Taiwan Univ., Taipei, Taiwan, R.O.C., 2013. [73] A. Richter, S. W Glunz, F. Werner, J. Schmidt, and A. Cuevas, “Improved Quantitative Description of Auger Recombination in Crystalline Silicon,” Phys. Rev. B, vol. 86, no. 16, pp. 165202-1–165202-14, Oct. 2012. [74] J. G. Simmons, 'Generalized formula for the electric tunneling effect between similar electrodes separated by a thin insulating film,' J. Appl. Phys, vol. 34, no. 6, pp. 1793–1803, June 1963. [75] M. Miyamoto, H. Ohta, Y. Kumagai, Y. Sonobe, K. Ishibashi, and Y. Tainaka, “Impact of Reducing STI-Induced Stress on Layout Dependence of MOSFET Characteristics,” IEEE Trans. Electron Devices, vol. 51, no. 3, pp. 440–443, Mar. 2004. [76] Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, C. H. Diaz, “Modeling Mechanical Stress Effect on Dopant Diffusion in Scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 30–38, Jan. 2005. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/58033 | - |
dc.description.abstract | 本篇論文主要藉由側邊擴散電流來討論其對於超薄氧化層p型及n型矽基板金氧半電容元件之周邊相關電流的影響與其應用。在論文的第二章,利用不同的元件閘極圖案的設計,來證明元件側邊的擴散電流在超薄氧化層p型矽基板金氧半電容元件中扮演了重要的角色,即反轉區電流的周邊相關現象係來自於側邊擴散電流的作用,透過側邊擴散電流的補充,元件邊緣的電子濃度較中間處大,使得氧化層壓降增加,以及電洞之蕭基位障下降,造成大量電洞電流流經元件周邊。同時,也可以同樣的概念來解釋金氧半電容與金氧半場效電晶體之閘極漏電流的差異。在論文的第三章,我們利用側邊擴散電流受溫度調變的特性,製作了金氧半穿隧溫度感測器,由於側邊擴散電流的影響,金氧半穿隧溫度感測器之反轉區電流亦呈現周邊相關的特性,此周邊相關之電流特性係無法以空乏區內熱激發電流來解釋,而電流對溫度的相依性亦呈現與熱激發電流不同的趨勢。藉由側邊擴散電流引起的邊緣電洞電流即可解釋周邊相關現象以及溫度相依性。在論文的第四章,我們亦利用側邊擴散電流來製作金氧半光二極體,透過比較不同氧化層厚度元件的光電流,我們發現當厚度越大,其光電流越大,此現象不能由傳統認為的邊緣空乏區光激發電流機制來解釋,利用TCAD模擬亦可知當厚度越大,其側邊延伸的空乏區寬度越小,即集光區越小,光電流理當應隨厚度增大而減小,但實驗觀察並非如此。如同溫度感測器,在文獻及本論文實驗中可知金氧半光二極體電流亦呈周邊相關特性,此一現象僅能由側邊擴散電流所引起的邊緣電洞電流來解釋。在論文的第五章,我們比較了p型和n型矽基板金氧半電容元件之電流特性,在n型矽基板金氧半元件中,由於其具與p型矽基板不同的能帶結構,故側邊擴散電流對於暗電流的影響並不顯著,然而對於光電流卻有極明顯的影響,造成光敏度在具較厚氧化層之元件中急劇上升,此一現象僅能由側邊擴散電流引發之氧化層壓降增加,並允許大量電子由金屬穿隧至矽基板來解釋。 | zh_TW |
dc.description.abstract | In this thesis, we demonstrate the importance of the lateral diffusion current in the current behavior of MOS(p) capacitor with ultrathin oxide and the applications by utilizing the lateral diffusion current. In chapter 2, through comparing the current phenomenon of MOS(p) capacitors with different gate patterns, we can verify that the lateral diffusion current plays an important role in the current characteristic of MOS(p) capacitor. In other words, the perimeter-dependent current behavior is caused by the lateral diffusion current. By the supplement of the lateral diffusion current, the electron concentration is higher in the edge region than in the bulk region, leading to the increase in the edge oxide voltage and smaller Schottky barrier height of holes which allows massive Schottky diode hole current to flow through the edge of the device. Furthermore, the concept of supplement of electrons can be used to explain the difference of gate leakage currents of MOSCAP(p) and NMOSFET. In chapter 3, due to the change of the lateral diffusion current with temperature, we make use of the lateral diffusion current to detect temperature in MOS(p) tunneling temperature sensor whose inversion current is perimeter-dependent. This perimeter-dependent current phenomenon cannot be explained by the thermal generation current in the depletion region, and the temperature dependence of current does not agree with the experimental data. Instead, the edge Schottky diode hole current can be used to well explain the current behavior. In chapter 4, we demonstrate MOS(p) photodiodes by utilizing the lateral diffusion currents. Through fabricating MOS(p) photodiodes with different oxide thicknesses, we find that when the oxide is thicker, the light current is larger. This cannot be explained by the conventional explanation, i.e., the edge photo-generation current in depletion region. Moreover, by using TCAD simulation, it is proved that the edge depletion width will decrease with thicker oxide, indicating that the collection region of light is smaller and the light current also should be smaller. Just like the MOS(p) tunneling temperature sensor, the perimeter-dependent current characteristic of MOS(p) photodiode can be found in some papers and experiments in chapter 4, and this phenomenon only can be explained by the edge Schottky diode hole current. In chapter 5, we compare the current characteristics of MOS(p) and MOS(n) capacitors. In MOS(n), due to its different band structures compared to MOS(p), the lateral diffusion cannot affect the dark current behavior but can influence the light current significantly, leading to strong sensitivity enhancement in the device with thicker oxide. This phenomenon only can be explained by the oxide voltage tuning, which introduce large electron direct tunneling current, induced by the lateral hole diffusion current. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T08:04:52Z (GMT). No. of bitstreams: 1 ntu-103-R02943054-1.pdf: 8387220 bytes, checksum: 3691c6a678b7d14412f054d26b284d40 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | Abstract (Chinese)……………………………………………………………………I
Abstract (English)……………………………………………………………………II Contents………………………………………………………………………………IV Figure Captions……………………………………………………………………VII Table Captions……………………………………………………………………XIII Chapter 1 Introduction………………………………………………………………1 1-1 Motivation……………………………………………………………………1 1-2 Anodization System…………………………………………………………3 1-3 Determination of Oxide Thickness…………………………………………5 1-4 Tunneling Mechanism in MOS Capacitors……………………………………7 1-5 TCAD Simulation……………………………………………………………9 1-6 Importance of Minority Carriers……………………………………………11 1-7 Summary……………………………………………………………………12 Chapter 2 Role of Lateral Diffusion Current in Current Characteristic of MOS(p) Capacitors under Inversion Region…………………………………………………16 2-1 Introduction………………………………………………………………16 2-2 Experimental Details and TCAD Simulation…………………………17 2-3 Results and Discussion……………………………………………………18 2-3-1 Current Behavior Overview……………………………………………18 2-3-2 Lateral Electron Distribution and Gradient……………………20 2-3-3 Impact of Lateral Diffusion Current in MOS(p)……………21 2-3-4 Gate Leakage Current of MOSCAP(p) and NMOSFET……………24 2-4 Summary……………………………………………………………………27 Chapter 3 MOS(p) Tunneling Temperature Sensor with Perimeter-Dependent Current Characteristic……………………………………37 3-1 Introduction…………………………………………………………………37 3-2 Experimental Details and TCAD Simulation…………………………38 3-3 Results and Discussion………………………………………………………40 3-3-1 Current Behavior Overview……………………………………………40 3-3-2 Lateral Electron Diffusion Current………………………………………41 3-3-3 Temperature-Sensing under Inversion Region……………………42 3-4 Summary……………………………………………………………………44 Chapter 4 MOS(p) Tunneling Photodiode by Utilizing Edge Schottky Barrier Height Modulation……………………………………………………………50 4-1 Introduction…………………………………………………………………50 4-2 Experimental Details and TCAD Simulation…………………………52 4-3 Results and Discussion………………………………………………………54 4-3-1 Contradiction of Proposed Models……………………………………54 4-3-2 Edge Schottky Barrier Height Modulation……………………………54 4-3-3 Pinned Oxide Field……………….……………………………………57 4-3-4 Dependencies on Area and Perimeter…………………………………59 4-3-5 Sensitivity………………………………………………………………61 4-4 Summary……………………………………………………………………62 Chapter 5 MOS(n) Capacitors with Ultrathin Oxides and Tunneling Photodiodes: A Lateral Diffusion Current Approach………………………………………………70 5-1 Introduction…………………………………………………………………70 5-2 Experimental Details…………………………………………………………71 5-3 Results and Discussion………………………………………………………71 5-3-1 Difference of Current Behaviors of MOS(p) and MOS(n)……………71 5-3-2 MOS(n) Tunneling Photodiode…………………………………………73 5-3-2-1 Operation Overview………………………………………………73 5-3-2-2 Oxide Voltage Tuning and Enhanced Sensitivity……………74 5-3-2-3 Dependencies on Area and Perimeter………………………………76 5-4 Summary……………………………………………………………………78 Chapter 6 Conclusions and Suggestions for Future Work……………84 6-1 Conclusions…………………………………………………………………84 6-2 Suggestions for Future Work…………………………………………………86 References…………………………………………………………………………90 Appendix A Detail Descriptions and Calibration of TCAD Simulation……………99 A-1 Physical Models and Parameters for Calibration…………99 A-2 Summary……………………………………………………………………104 Appendix B Negative Accumulation Capacitance in MOS(p) with Ultrathin Oxide………………………………108 B-1 Introduction…………………………………………………………………108 B-2 Device Fabrication and Simulation…………………………………………109 B-3 Results and Discussion……………………………………………………110 B-3-1 Substrate Doping Concentration Effect………………………………111 B-3-2 Gate Length Effect……………………………………………………112 B-4 Conclusion…………………………………………………………………112 Referecnes…………………………………………………………………………116 | |
dc.language.iso | en | |
dc.title | 側向擴散電流對超薄氧化層金氧半元件之反轉區電流特性影響與其相關應用 | zh_TW |
dc.title | Effect of Lateral Diffusion Current in Inversion I-V Characteristic of MOS Devices with Ultrathin Oxide and Its Applications | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 鄭晃忠(Huang-Chung Cheng),吳肇欣(Chao-Hsin Wu),李峻霣(Jiun-Yun Li) | |
dc.subject.keyword | 超薄氧化層,金氧半元件,側邊擴散電流,蕭基位障調變,金氧半穿隧溫度感測器,金氧半光二極體, | zh_TW |
dc.subject.keyword | ultrathin oxide,MOS devices,lateral diffusion current,Schottky barrier height modulation,MOS tunneling temperature sensor,MOS photodiode, | en |
dc.relation.page | 116 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-06-27 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-103-1.pdf 目前未授權公開取用 | 8.19 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。