請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57651完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 莊東漢(Tung-Han Chuang) | |
| dc.contributor.author | Yu-Ting Shih | en |
| dc.contributor.author | 施昱廷 | zh_TW |
| dc.date.accessioned | 2021-06-16T06:56:05Z | - |
| dc.date.available | 2024-12-31 | |
| dc.date.copyright | 2014-08-05 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-07-18 | |
| dc.identifier.citation | [1] T.-H. Chuang, C.-H. Tsai, H.-C. Wang, C.-C. Chang, C.-H. Chuang, J.-D. Lee, H.-H. Tsai, Effects of Annealing Twins on the Grain Growth and Mechanical Properties of Ag-8Au-3Pd Bonding Wires, Journal of Elec Materi, 41 (2012) 3215-3222.
[2] T.-H. Chuang, H.-C. Wang, C.-H. Chuang, J.-D. Lee, H.-H. Tsai, Effect of Annealing Twins on Electromigration in Ag-8Au-3Pd Bonding Wires, Journal of Elec Materi, 42 (2013) 545-551. [3] T.-H. Chuang, H.-C. Wang, C.-H. Chuang, H.-J. Lin, J.-D. Lee, H.-H. Tsai, Surface Reconstruction of an Annealing Twinned Ag-8Au-3Pd Alloy Wire Under Current Stressing, Metall and Mat Trans A, 44 (2013) 5106-5112. [4] T.-H. Chuang, C. Che-Cheng, C. Chien-Hsun, L. Jun-Der, T. Hsing-Hua, Formation and Growth of Intermetallics in an Annealing-Twinned Ag-8Au-3Pd Wire Bonding Package During Reliability Tests, Components, Packaging and Manufacturing Technology, IEEE Transactions on, 3 (2013) 3-9. [5] Y.-K. Lee, Y.-H. Ko, J.-K. Kim, C.-W. Lee, S. Yoo, The effect of intermetallic compound evolution on the fracture behavior of Au stud bumps joined with Sn-3.5Ag solder, Electron. Mater. Lett., 9 (2013) 31-39. [6] M.-S. Shin, Y.-H. Kim, Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads, Journal of Elec Materi, 32 (2003) 1448-1454. [7] M.-H. Jeong, Y.-B. Park, Interfacial reaction kinetics in Au stud/Sn bumps during annealing and current stressing, Current Applied Physics, 11 (2011) S124-S127. [8] R.R. Tummala, E.J. Rymaszewski, A.G. Klopfenstein, Microelectronics Packaging Handbook: Technology Drivers, Chapman & Hall, 1997. [9] 莊東漢•黃漢邦•謝國煌•蔡豐羽•陳炳宏•鄭晃忠, 平面顯示器概論, 高立, 2008. [10] R.R. Tummala, Fundamentals of Microsystems Packaging, Mcgraw-hill, 2001. [11] J.H. Lau, Ball Grid Array Technology, McGraw-Hill, 1995. [12] K.N. Ritz, W. Stacy, E.K. Broadbent, The Microstructure of Ball Bond Corrosion Failures, Reliability Physics Symposium, 1987. 25th Annual, 1987, pp. 28-33. [13] M.-H. Lue, C.-T. Huang, S.-T. Huang, K.-C. Hsieh, Bromine- and chlorine-induced degradation of gold-aluminum bonds, Journal of Elec Materi, 33 (2004) 1111-1117. [14] T. Uno, K. Tatsumi, Thermal reliability of gold–aluminum bonds encapsulated in bi-phenyl epoxy resin, Microelectronics Reliability, 40 (2000) 145-153. [15] C. Goh, W. Chong, T. Lee, C. Breach, Corrosion Study and Intermetallics Formation in Gold and Copper Wire Bonding in Microelectronics Packaging, Crystals, 3 (2013) 391-404. [16] T. Uno, T. Yamada, Improving humidity bond reliability of copper bonding wires, Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, pp. 1725-1732. [17] T. Uno, Bond reliability under humid environment for coated copper wire and bare copper wire, Microelectronics Reliability, 51 (2011) 148-156. [18] C.-F. Yu, C.-M. Chan, L.-C. Chan, K.-C. Hsieh, Cu wire bond microstructure analysis and failure mechanism, Microelectronics Reliability, 51 (2011) 119-124. [19] C.L. Gan, E.K. Ng, B.L. Chan, U. Hashim, F.C. Classe, Technical barriers and development of Cu wirebonding in nanoelectronics device packaging, J. Nanomaterials, 2012 (2012) 96-96. [20] S. Peng, H. Seki, P. Chen, S. Zenbutsu, S. Itoh, L. Huang, N. Liao, B. Liu, C. Chen, W. Tai, A. Tseng, An evaluation of effects of molding compound properties on reliability of Cu wire components, Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 2011, pp. 363-369. [21] C. Jong-Soo, Y. Kyeong-Ah, H. Sung-Jae, M. Jeong-Tak, L. Yong-Je, H. Wongil, P. Hanki, H. Seung-Weon, S. Seong-Bum, K. Suk-Hoon, O. Kyu-Hwan, Pd effects on the reliability in the low cost Ag bonding wire, Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th, 2010, pp. 1541-1546. [22] C.W. Tan, A.R. Daud, M.A. Yarmo, Corrosion study at Cu–Al interface in microelectronics packaging, Applied Surface Science, 191 (2002) 67-73. [23] K. DeHaven, J. Dietz, Controlled collapse chip connection (C4)-an enabling technology, Electronic Components and Technology Conference, 1994. Proceedings., 44th, 1994, pp. 1-6. [24] R.R. Tummala, E.J. Rymaszewski, Microelectronics packaging handbook, Van Nostrand Reinhold, 1989. [25] P. Garrou, C. Bower, P. Ramm, Handbook of 3D Integration: Volume 1 - Technology and Applications of 3D Integrated Circuits, Wiley, 2011. [26] J.U. Knickerbocker, P.S. Andry, L.P. Buchwalter, A. Deutsch, R.R. Horton, K.A. Jenkins, Y.H. Kwark, G. McVicker, C.S. Patel, R.J. Polastre, C. Schuster, A. Sharma, S.M. Sri-Jayantha, C.W. Surovic, C.K. Tsang, B.C. Webb, S.L. Wright, S.R. McKnight, E.J. Sprogis, B. Dang, Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection, IBM Journal of Research and Development, 49 (2005) 725-753. [27] Y. Akasaka, Three-dimensional IC trends, Proceedings of the IEEE, 74 (1986) 1703-1714. [28] J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C.S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, S.L. Wright, 3D silicon integration, Electronic Components and Technology Conference, 2008. ECTC 2008. 58th, 2008, pp. 538-543. [29] K. Sakuma, P.S. Andry, B. Dang, J. Maria, C.K. Tsang, C. Patel, S.L. Wright, B. Webb, E. Sprogis, S.K. Kang, R. Polastre, R. Horton, J.U. Knickerbocker, 3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections, Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th, 2007, pp. 627-632. [30] H. Yuan-Kai, L. Hsu-Chieh, W. Lee, C. Yao-Wen, C. Chen-Feng, I.J. Lin, S. Chin-Fang, Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs, Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 33 (2014) 224-236. [31] T. Tschan, An Overview of Flip-Chip Technology, ChipScale Review, (2001). [32] G.R. Blackwell, The Electronic Packaging Handbook, Taylor & Francis, 1999. [33] S.W. Jung, J.P. Jung, Y. Zhou, Characteristics of Sn–Cu Solder Bump Formed by Electroplating for Flip Chip, Electronics Packaging Manufacturing, IEEE Transactions on, 29 (2006) 10-16. [34] R. Kiumi, S. Takeda, J. Yoshioka, F. Kuriyama, N. Saito, Composition control for lead-free alloy electroplating on flip chip bumping, Electronic Components and Technology Conference, 2005. Proceedings. 55th, 2005, pp. 120-126 Vol. 121. [35] D.R. Frear, Materials issues in area-array microelectronic packaging, JOM, 51 (1999) 22-27. [36] B. Neveu, F. Lallemand, G. Poupon, Z. Mekhalif, Electrodeposition of Pb-free Sn alloys in pulsed current, Applied Surface Science, 252 (2006) 3561-3573. [37] S.-T. Wang, Integrating the Taguchi Method and the Multiattribute Decision-making Method to Optimize the Surface Mount Technology Solder Paste Printing Thickness Process, Proceedings of the Institution of Mechanical Engineers, Part B: Journal of Engineering Manufacture, (2013). [38] X. Deng, M. Koopman, N. Chawla, K.K. Chawla, Young’s modulus of (Cu, Ag)–Sn intermetallics measured by nanoindentation, Materials Science and Engineering: A, 364 (2004) 240-243. [39] J.S. Kang, R.A. Gagliano, G. Ghosh, M.E. Fine, Isothermal solidification of Cu/Sn diffusion couples to form thin-solder joints, Journal of Elec Materi, 31 (2002) 1238-1243. [40] S. Kumar, J. Jung, Mechanical and electronic properties of Ag3Sn intermetallic compound in lead free solders using ab initio atomistic calculation, Materials Science and Engineering: B, 178 (2013) 10-21. [41] I. Kovács, G. Vörös, On the mathematical description of the tensile stress-strain curves of polycrystalline face centered cubic metals, International Journal of Plasticity, 12 (1996) 35-43. [42] W.-m. Tang, A.-q. He, Q. Liu, D.G. Ivey, Solid state interfacial reactions in electrodeposited Cu/Sn couples, Transactions of Nonferrous Metals Society of China, 20 (2010) 90-96. [43] F. Bartels, J.W. Morris, G. Dalke, W. Gust, Intermetallic phase formation in thin solid-liquid diffusion couples, Journal of Elec Materi, 23 (1994) 787-790. [44] C.K. Chung, J.-G. Duh, C.R. Kao, Direct evidence for a Cu-enriched region at the boundary between Cu6Sn5 and Cu3Sn during Cu/Sn reaction, Scripta Materialia, 63 (2010) 258-260. [45] C.R. Kao, Microstructures developed in solid-liquid reactions: using Cu-Sn reaction, Ni-Bi reaction, and Cu-In reaction as examples, Materials Science and Engineering: A, 238 (1997) 196-201. [46] V. Simić, Ž. Marinković, Room temperature interactions in Ag-metals thin film couples, Thin Solid Films, 61 (1979) 149-160. [47] G. Humpston, D.M. Jacobson, S.P.S. Sangha, Diffusion soldering for electronics manufacturing, Endeavour, 18 (1994) 55-60. [48] J.F. Li, P.A. Agyakwa, C.M. Johnson, Kinetics of Ag3Sn growth in Ag–Sn–Ag system during transient liquid phase soldering process, Acta Materialia, 58 (2010) 3429-3443. [49] T.L. Su, L.C. Tsao, S.Y. Chang, T.H. Chuang, Morphology and growth kinetics of Ag3Sn during soldering reaction between liquid Sn and an Ag substrate, J. of Materi Eng and Perform, 11 (2002) 365-368. [50] T. Takenaka, M. Kajihara, N. Kurokawa, K. Sakamoto, Reactive diffusion between Ag–Au alloys and Sn at solid-state temperatures, Materials Science and Engineering: A, 427 (2006) 210-222. [51] T. Sakama, M. Kajihara, Influence of Ag on Kinetics of Solid-State Reactive Diffusion between Pd and Sn, MATERIALS TRANSACTIONS, 50 (2009) 266-274. [52] T. Sakama, M. Kajihara, Kinetics of reactive diffusion between Pd–Ag alloys and Sn at solid-state temperatures, Journal of Alloys and Compounds, 475 (2009) 608-613. [53] G. Sharma, C.M. Eichfeld, S.E. Mohney, Intermetallic growth between lead-free solders and palladium, Journal of Elec Materi, 32 (2003) 1209-1213. [54] T. Takenaka, M. Kajihara, N. Kurokawa, K. Sakamoto, Reactive diffusion between Pd and Sn at solid-state temperatures, Materials Science and Engineering: A, 406 (2005) 134-141. [55] R. Ravi, A. Paul, Diffusion and growth mechanism of phases in the Pd-Sn system, J Mater Sci: Mater Electron, 23 (2012) 2306-2310. [56] R. Kubiak, Woz.xl, M. lcyrz, Refinement of the crystal structures of AuSn4 and PdSn4, Journal of the Less Common Metals, 97 (1984) 265-269. [57] H. Okamoto, Desk Handbook: Phase Diagrams for Binary Alloys, ASM International, 2000. [58] M. Hillert, Diffusion and interface control of reactions in alloys, MTA, 6 (1975) 5-19. [59] L.C.-K. Liau, B.S.-C. Chen, Process optimization of gold stud bump manufacturing using artificial neural networks, Expert Systems with Applications, 29 (2005) 264-271. [60] J. Jordan, Gold stud bump in flip-chip applications, Electronics Manufacturing Technology Symposium, 2002. IEMT 2002. 27th Annual IEEE/SEMI International, 2002, pp. 110-114. [61] Y. Myung-Jin, H. Jin-Sang, K. Woonseong, J. Kyung Woon, P. Kyung-Wook, Highly reliable non-conductive adhesives for flip chip CSP applications, Electronics Packaging Manufacturing, IEEE Transactions on, 26 (2003) 150-155. [62] L. Daoqiang, C.P. Wong, A study of contact resistance of conductive adhesives based on anhydride-cured epoxy systems, Components and Packaging Technologies, IEEE Transactions on, 23 (2000) 440-446. [63] L. Daoqiang, C.P. Wong, Development of solder replacement conductive adhesives with stable resistance and superior impact performance, Adhesive Joining and Coating Technology in Electronics Manufacturing, 2000. Proceedings. 4th International Conference on, 2000, pp. 110-116. [64] C. Ghosh, Interdiffusion study in binary gold–tin system, Intermetallics, 18 (2010) 2178-2182. [65] P.G. Kim, K.N. Tu, Fast dissolution and soldering reactions on Au foils, Materials Chemistry and Physics, 53 (1998) 165-171. [66] X. Guowei, P. Chan, J. Cai, A. Teng, M. Yuen, The effect of Cu stud structure and eutectic solder electroplating on intermetallic growth and reliability of flip-chip solder bump, Electronic Components & Technology Conference, 2000. 2000 Proceedings. 50th, 2000, pp. 54-59. [67] X. Guo-Wei, P.C.H. Chan, A. Teng, C. Jian, M.M.F. Yuen, Effect of Cu stud microstructure and electroplating process on intermetallic compounds growth and reliability of flip-chip solder bump, Components and Packaging Technologies, IEEE Transactions on, 24 (2001) 682-690. [68] P. Schnederle, M. Adamek, I. Szendiuch, Effect of nitrogen atmosphere on the soldering process for different types of lead-free solders, Electronics Technology (ISSE), 2012 35th International Spring Seminar on, 2012, pp. 201-206. [69] I. Qin, X. Hui, H. Clauberg, R. Cathcart, V.L. Acoff, B. Chylak, H. Cuong, Wire bonding of Cu and Pd coated Cu wire: Bondability, reliability, and IMC formation, Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st, 2011, pp. 1489-1495. [70] T. Lei-Jun, H. Hong-Meng, Z. Yue-Jia, L. Yuet-Mun, L. Che-Wei, Investigation of Palladium Distribution on the Free Air Ball of Pd-coated Cu wire, Electronics Packaging Technology Conference (EPTC), 2010 12th, 2010, pp. 777-782. [71] Z. Binhai, Q. Kaiyou, T. Wang, C. Yuqi, M. Zhao, F. Xiangquan, W. Jiaji, Behaviors of palladium in palladium coated copper wire bonding process, Electronic Packaging Technology & High Density Packaging, 2009. ICEPT-HDP '09. International Conference on, 2009, pp. 662-665. [72] G. Bianchi, P. Longhi, Copper in sea-water, potential-pH diagrams, Corrosion Science, 13 (1973) 853-864. [73] E.M. Sherif, S.-M. Park, Effects of 1,5-Naphthalenediol on Aluminum Corrosion as a Corrosion Inhibitor in 0.50 M NaCl, Journal of The Electrochemical Society, 152 (2005) B205-B211. [74] K. Zeng, R. Stierman, T.-C. Chiu, D. Edwards, K. Ano, K.N. Tu, Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability, Journal of Applied Physics, 97 (2005) -. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57651 | - |
| dc.description.abstract | 近年來由於金價高漲,迫使產界與學界積極開發取代金打線的材料,銀合金線的發明,不管是在成本或可靠度上,皆展現優秀的性質,也為封裝產業提供一個更佳的選擇。然而半導體上游微顯影技術不斷提升,使得日常生活3C產品性能不斷進步,為了延續摩爾定律,3D IC技術被發明,其封裝技術中,需利用金屬凸塊。但現今主流技術如電鍍法,造成汙染時有所聞,而Stud Bump技術不需用到電鍍技術,符合現今環保觀念,但傳統使用材料為金,本研究評估將金轉換為銀合金,利用銀合金線製造出高可靠度的銀合金凸塊。
本研究第一部分為評估現今封裝打線電化學性質,由極化曲線的腐蝕電位與腐蝕電流判斷其抗腐蝕性,結果得知鋁線抗腐蝕性最差,鍍鈀銅線燒結成球後,會有鈀層擴散入內的情形,至於銀加入貴金屬金與鈀後,抗腐蝕性大幅提升,抗腐蝕性順序為:Ag-8Au-3Pd > Ag-3>Pd>Pd-Coated Cu > Al。 本研究第二部分為模擬Stud Bump界面,傳統金凸塊與銲錫(Sn-3Ag-0.5Au)反應後,金會大量擴散入銲錫中,生成AuSn4,導致「金脆現象」,導致界面破壞,而銅與銲錫反應後,介金屬層生成厚度太薄,且介金屬會有裂縫,整體可靠度不佳,銀合金與銲錫反應後,界面單純,只有Ag3Sn,整體厚度介於金與銅之間,介金屬成長穩定,但在200℃長時間時效後,錫原子會越過Ag3Sn,與銀合金金或鈀原子結合形成AuSn4或PdSn4,且界面會出現裂縫。 | zh_TW |
| dc.description.abstract | These years, the higher gold price has forced a number of groups in industry and academy to develop new wire bonding materials to replace the gold wire. The newly developing Ag alloy wire has a great deal of advantages include either cost or reliability and is a better approach for the electronic packaging industry doubtlessly. Thanks to the continually improving lithography of upstream, the function of 3C products in our daily life keeps on improving. To prolong Moore’s Law, 3D IC was invented, and the metal bumps are necessitated during packaging. However, the prevailing method such as electroplating has raised a few pollution issues. In contrast, Stud Bump rules out electroplating and fulfills the environment-friendly need. This research assesses the possibility if the Ag alloy wire could substitute the traditional gold wire to make highly reliable metal bumps.
In this research, the first part is to assess the electrochemical property of current bonding wire, the corrosion potential and current on the polarization curve decide the corrosion resistance. The results show that the Al wire has the poorest corrosion resistance, and after EFO burning, the Pd layer of Pd-coated Cu wire will diffuse inside the core. Different to them, Ag can gain much higher corrosion resistance after alloying with noble metals Pd and Au. The corrosion resistance trend is : Ag-8Au-3Pd > Pd-Coated Cu > Ag-3Pd > Al. Second part is the simulation of Stud Bump interface. In the results, Au will diffuse into Sn layer abundantly to form AuSn4 after the reaction between traditional gold bump and solder (Sn-3Ag-0.5Au), gold embrittlement and the interface will result crack. It also shows that in the reaction between Cu and solder, the formation breaks with cracks because the IMC is too thin, and the reliability is poor. In contrast, the interface between Ag alloy and solder after reacting is simple - the only IMC Ag3Sn forms stably, and the average thickness is between the two reactions above. However, after aging for a long time at 200℃, Sn will go across Ag3Sn and form AuSn or PdSn4 with Au and Pd, furthermore, and results in cracks. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T06:56:05Z (GMT). No. of bitstreams: 1 ntu-103-R01527057-1.pdf: 17621517 bytes, checksum: 093a3ff722184d00e9600055cb802019 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | 摘要 i
Abstract ii 目錄 iv 圖目錄 vi 表目錄 xi 第一章 前言 1 1.1 研究背景 1 1.2 研究動機 2 第二章 文獻回顧 5 2.1電子構裝及發展 5 2.2 封裝打線腐蝕 9 2.3覆晶接合 14 2.4 覆晶凸塊製程 17 2.5介金屬性質文獻回顧 20 2.5.1 Cu-Sn系統 20 2.5.2 Ag-Sn系統 22 2.5.3 Pd-Sn系統 23 表2- 1覆晶技術常見IMC與材料性質 24 2.6界面反應動力學 29 2.6.1界面控制反應 30 2.6.2擴散控制反應 31 2.7 Stud Bump發展 32 第三章 實驗方法與步驟 36 3.1 封裝打線極化曲線量測 36 3.2 Stud Bump界面反應 38 3.2.2 模擬Stud Bump界面試片製作 38 第四章 結果與討論 44 4.1 封裝打線極化曲線 44 4.1.1 各式封裝打線抗腐蝕性比較 44 4.1.2 鍍鈀銅線抗腐蝕性討論 46 4.1.3 貴金屬添加對銀合金線抗腐蝕性影響 47 表4- 3 標準電位 50 4.1.4 線材腐蝕表面分析 51 4.2 Stud Bump界面 54 4.2.1 金Stud Bump界面 57 4.2.2 銅Stud Bump界面 61 4.2.3 銀合金Stud Bump界面 68 4.3 介金屬層厚度與動力學分析 86 第五章 結論 92 參考文獻 93 | |
| dc.language.iso | zh-TW | |
| dc.subject | 極化曲線 | zh_TW |
| dc.subject | 腐蝕 | zh_TW |
| dc.subject | 銀合金線 | zh_TW |
| dc.subject | 凸塊 | zh_TW |
| dc.subject | 銲錫 | zh_TW |
| dc.subject | 介金屬 | zh_TW |
| dc.subject | Inter-Metallic Compounds(IMC) | en |
| dc.subject | Corrosion | en |
| dc.subject | Polarization Curve | en |
| dc.subject | Bump | en |
| dc.subject | Solder | en |
| dc.subject | Ag-alloy wire | en |
| dc.title | 銀合金銲球凸塊覆晶組裝可行性評估 | zh_TW |
| dc.title | Evaluations of the Applicability of Ag-alloy Stud Bump on Flip-Chip Assembly | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 碩士 | |
| dc.contributor.oralexamcommittee | 薛富盛(F.S.Shieu),蔡幸樺(C.-H. Tsai),李俊德(J.-D. Lee) | |
| dc.subject.keyword | 銀合金線,腐蝕,極化曲線,凸塊,銲錫,介金屬, | zh_TW |
| dc.subject.keyword | Ag-alloy wire,Corrosion,Polarization Curve, Bump,Solder,Inter-Metallic Compounds(IMC), | en |
| dc.relation.page | 101 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-07-21 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
| 顯示於系所單位: | 材料科學與工程學系 | |
文件中的檔案:
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-103-1.pdf 未授權公開取用 | 17.21 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。
