請用此 Handle URI 來引用此文件：
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57612完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.advisor | 高振宏(C. Robert Kao) | |
| dc.contributor.author | Cheng-Chieh Li | en |
| dc.contributor.author | 李澄傑 | zh_TW |
| dc.date.accessioned | 2021-06-16T06:54:04Z | - |
| dc.date.available | 2014-08-14 | |
| dc.date.copyright | 2014-08-14 | |
| dc.date.issued | 2014 | |
| dc.date.submitted | 2014-07-21 | |
| dc.identifier.citation | [1] http://blogs.mentor.com/happyholden/blog/tag/pcb/
[2] http://eda360insider.wordpress.com/2011/10/27/3d-thursday-generation-jumping-2-5d-xilinx-virtex-7-2000t-fpga-delivers-1954560-logic-cells-using-6-8-billion-transistors/ [3] A. Agerwala, and M. Gupta, IBM Journal of Research and Development, 50, p.173-180, 2006. [4] T. C. Chen, Where Si-CMOS is Going: Trendy Hype vs Real Technology, ISSCC, 2006. [5] J. U. Knickerbocker, P. S. Andry, L. P. Buchwalter, A. Deutsch, R. R. Horton, K. A. Jenkins, Y. H. Kwark, G. McVicker, C. S. Patel, R. J. Polastre, C. D. Schuster, A. Sharma, S. M. Sri-Jayantha, C. W. Surovic, C. K. Tsang, B. C. Webb, S. L. Wright, S. R. McKnight, E. J. Sprogis, and B. Dang, IBM Journal of Research and Development, 49, p.725-753, 2005. [6] http://www.pti.com.tw/ptiweb/D0008.aspx?p=D&c=D8&language=C [7] A. Munding, H. Hubner, A. Kaiser, S. Penka, P. Benkart, and E. Kohn, Wafer Level 3-D ICs Process Technology, Springer Science & Business Media, New York, 2008. [8] P. Garrou, Future ICs Go Vertical, Semiconductor International, 2005. [9] J. F. Li, P. A. Agyakwa, and C. M. Johnson, Acta Materialia, 59, p.1198-1211, 2011. [10] S. K. Kang, W. K. Choi, D. Y. Shih, D. W. Henderson, T. Gosselin, A. Sarkhel, C. Goldsmith, and K. J. Puttlitz, JOM, 55, p.61-65, 2003. [11] K. Zeng, and K. N. Tu, Materials Science and Engineering: R: Reports, 38, p.55-105, 2002. [12] F. Ochoa, J. J. Williams, and N. Chawla, Journal of Electronic Materials, 32, p.1414-1420, 2003. [13] P. Kettner, B. Kim, S. Pargfrieder, and S. Zhu, Proceeding of 2008 International Conference on Electronic Packaging Technology & High Density Packaging, 2008. [14] S. W. Yoon, 3D Integration with TSV Technology, SEMICON Singapore, 2008. [15] M. Puech, J. M. Thevenoud, J. M. Gruffat, N. Launay, N. Arnal, and P. Godinat, Proceeding of Symposium on Design, Test, Integration & Packaging of MEMS/MOEMS, 2008. [16] N. Ranganathan, E. Liao, L. Linn, W. Lee, O. K. Navas, V. Kripesh, and N. Balasubramanian, Proceeding of IEEE Electronic Components and Technology Conference, 2008. [17] S. Arkalgud, Proceeding of SEMATECH/ISMI Symposium, 2009. [18] P. Ramm, M. J. Wolf, A. Klumpp, R. Wieland, B. Wunderle, and B. Michel, Proceeding of IEEE Electronic Components and Technology Conference, 2008. [19] J. J. Tang, From 2D Soc to 3D IC, Industrial Technology Research Institute Taiwan, 2009. [20] Market Trends for 3D Stacking EMC 3D, Yole Developpment, 2007. [21] K. Takahashi, H. Terao, Y. Tomita, Y. Yamaji, M. Hoshino, T. Sato, T. Morifuji, M. Sunohara, and M. Bonkohara, Japanese Journal of Applied Physics, 40, p.3032-3037, 2001. [22] T. S. Jung, Samsung Memory Technology and Solutions Roadmap, Samsung, 2008. [23] J. F. Shackelford, W. Alexander, CRC Materials Science and Engineering Handbook, Third Edition, CRC Press, New York, 2001. [24] H. P. R. Frederikse, R. J. Fields, A. Feldman, Journal of Applied Physics, 72, p.2879-2882, 1992. [25] W. M. Haynes and David R. Lide, Handbook of Chemistry and Physics 92nd, CRC Press, New York, 2012. [26] E. Gunnas, A. Olsen, and H. Hero, Journal of microscopy, 185, p.188-198, 1997. [27] K.L. Erickson, P.L. Hopkins, and P.T. Vianco, Journal of Electronic Materials, 27, p.1177-1192, 1998. [28] K.N. Tu, Materials Letters, 1, p.6-10, 1982. [29] H. Y. You, Y. S. Lee, S. K. Lee, and J. S. Kang, Proceedings of the 61st ECTC, 2011. [30] H. Xu,V. L. Acoff, C. Liu, V. V. Silberschmidt, and Z. Chen, Proceedings of the 61st ECTC 2011. [31] K. Yoneta, R. Sato, Y. Iwata, K. Atsumi, K. Okamoto, Y. Satio, and T. Shigemoto, Proceedings of the 64th ECTC, 2014. [32] C. M. Chen, and S. W. Chen, Acta Materialia, 50, p.2461-2469, 2002. [33] D. C. William, Materials Science and Engineering An Introduction 7th, John Wiley & Sons, Inc., 2007 [34] M. E. Glicksman, Diffusion in solids: field theory, solid-state principles and applications, Wiley, New York, 2000. [35] Dektak 6M Manual [36] R. Karmhag, G. Niklasson and M. Nygren, Journal of Applied Physics, 85, p. 1186, 1999. [37] Y. Nabeta, Y. Saitoh, S. Sawada, Y. Hattori, T. Tamai, Proceedings of the 55th IEEE Holm Conference on Electrical Contacts, pp.176-181, 2009. [38] C. E. Ho, S. C. Yang, and C. R. Kao, Journal of Materials Science: Materials in Electronics, 18, p155-174, 2007. [39] H. Y. Chuang, T. L. Yang, M. S. Kuo, Y. J. Chen, J. J. Yu, C. C. Li, and C. R. Kao, IEEE Transactions on Device and Materials Reliability, 12, p.233-240, 2012. [40] H.Y. Chuang, J.J. Yu, M.S. Kuo, H.M. Tong, and C.R. Kao, Scripta Materialia, 66, p.171-174, 2012. [41] J. A. van Beek, S. S. Stolk, and F. J. J. van Loo, Zeitschrift Fur Metallkunde, 73, p.439-444, 1982. [42] S. W. Chen, C. M. Chen and W. C. Liu, Journal of Electronic Materials, 27, 1193 (1998) [43] C. M. Liu, M.S. Thesis, National Central University, Taiwan (2000) [44] G. F. V. Voort, ASM Handbook: Volume 9: Metallography And Microstructures, 9th ed., ASM International, Materials Park, OH, 1985. [45] S. Arai, H. Akatsuka, and N. Kaneko, Journal of The Electrochemical Society, 150, C730-764, 2003. [46] S.Y. Jang, J. Wolf, O. Ehrmann, H. Gloor, H. Reichl, and K.W. Paik, IEEE Transactions on Electronics Packaging Manufacturing, 25, p.193-202, 2002. [47] B. Neveu , F. Lallemand, G. Poupon, and Z. Mekhalif, Applied Surface Science, 252, p. 3561–3573, 2006. [48] C. Ghosh, Journal of Materials Science: Materials in Electronics, 24, P. 2558-2561, 2013. [49] L. Yin and P. Borgesen, Journal of Materials Research, 26, p.455–466, 2011. [50] K. N. Tu, Acta Materialia, 21, 347-354, 1973. [51] K. Zeng., R. Stierman, T. C. Chiu, D. Edwards, K. Ano, and K. N. Tu, Journal of Applied Physics, 97, 024508, 2005. [52] J. Y. Kim, and J. Yu, Applied Physics Letters, 92, 092109, 2008. [53] J. Yu, and J. Y. Kim, Acta Materialia, 56, p.5514-5523, 2008. | |
| dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57612 | - |
| dc.description.abstract | 近年來半導體產業的發展逐漸落後於莫爾定律的預期，透過發展三維立體構裝 (3D IC) 技術以持續提供半導體產業發展的動能儼然成為各界共識。在眾多發展中的3D IC 封裝技術中，具微小銲料凸塊之晶片接合法是相當受到矚目的構裝方式。然而3D IC元件內之銲點尺寸非常微小，因此接點空間受限Space confinement所導致的界面反應特徵勢必與傳統銲點不同。本研究將針對此種微小接點因界面反應誘發之接點體積收縮(Volume Shrinkage)效應，進行理論分析與實驗量測。從理論分析中得知當Cu與Sn反應形成Cu6Sn5介金屬(Intermetallic Compound)會伴隨著5%理論體積收縮值，而Cu3Sn與Ni3Sn4反應則分別對應7.5%與11.3%收縮值。因此本實驗利用表面輪廓儀對Ni/Sn/Ni、Ni/Sn-Ag/Ni以及Cu/Sn/Cu於180℃熱處理下進行試片體積之監測，並以SEM觀測對應之微結構變化。最後結果顯示，接點中之體積收縮將可能誘發接點內應力以及結構缺陷，對接點強度將具有相當大的影響，本研究係首次以完整的實驗結果證明該效應的存在。 | zh_TW |
| dc.description.abstract | Imminent ending of Moore’s law is the most critical issue threatening the continuing development of semiconductor industry. The strategy of consensus in order to go beyond Moore’s law is through the Three-Dimensional Integrated Circuit (3D IC) architecture. Among many 3D IC integration schemes under development today, solder micro-bumping is a very promising one. Due to the extremely small size of solder joints in 3D IC packages, interfacial reaction features are quite different to that in the conventional solder joints. The space confinement behavior must be considered in the soldering reactions. In this proposal, data analysis and experimental implementation of the volume shrinkage induced by interfacial reaction in micro joints is investigated. Theoretically, there is a 5% shrinkage in volume to produce Cu6Sn5 from the reaction between Cu and Sn. The shrinkages for Cu3Sn and Ni3Sn4 are 7.5% and 11.3%, respectively. Consequently, micro joints would be in highly stressed states and prone to failure. Experimentally, stylus surface profilometer and SEM are carried out to measure the actual volume shrinkages and observe microstructure for Ni/Sn/Ni, Ni/Sn-Ag/Ni, and Cu/Sn/Cu sandwich structures during an isothermal aging at 180℃. The results show that the internal stress and the forming of voids in micro joints during solid state aging might induce potential reliability issues. It is the first time that the reaction induced volume shrinkage is experimentally measured in common solder system. Theoretical analysis and experimental evidence are presented in this proposal to illustrate these issues, and implications based on the findings will be also discussed. | en |
| dc.description.provenance | Made available in DSpace on 2021-06-16T06:54:04Z (GMT). No. of bitstreams: 1 ntu-103-F98527046-1.pdf: 3180375 bytes, checksum: c1f93c06b66121e664c5f2202ab05987 (MD5) Previous issue date: 2014 | en |
| dc.description.tableofcontents | ACKNOWLEGEMENT
摘要 I ABSTRACT II CONTENTS IV LIST OF FIGURES VI LIST OF TABLES X 1.0 INTRODUCTION 1.1 Backgroung Introduction 1 1.2 Definition and Causes of Volume Shrinkage 6 1.3 Issues Arising from Volume Shrinkage 10 1.4 Aims of the Thesis 16 2.0 EXPERIMENTAL DETAILS 2.1 Sample Preparation and Experimental Procedure 17 2.2 Alpha-step measurement 21 2.3 Alpha-step measurement of pure Sn and pure Ni 26 3.0 RESULTS AND DISCUSSION 3.1 Volume Shrinkage of Ni/Sn/Ni Reactions 29 3.2 Effects of Ag Addition: Volume Shrinkage of Ni/Sn-Ag/Ni Reactions 41 3.3 The Model of Volume Shrinkage in Ni-Sn System 52 3.4 Microstructure evolution for void formation during IMC Impingement 56 3.5 Volume shrinkage related to complex reaction mechanisms: Cu/Sn/Cu 60 4.0 SUMMARY 67 Reference 69 Curriculum Vitae 73 | |
| dc.language.iso | en | |
| dc.subject | 三維立體構裝 | zh_TW |
| dc.subject | 顯微結構 | zh_TW |
| dc.subject | 體積收縮 | zh_TW |
| dc.subject | 孔洞形成 | zh_TW |
| dc.subject | 介金屬反應 | zh_TW |
| dc.subject | voids formation | en |
| dc.subject | 3D IC | en |
| dc.subject | volume shrinkage | en |
| dc.subject | microstructure | en |
| dc.subject | interfacial reaction | en |
| dc.title | 微接點中因界面反應引發之體積收縮行為 | zh_TW |
| dc.title | Volume Shrinkage Induced by Interfacial Reaction In Micro Joints | en |
| dc.type | Thesis | |
| dc.date.schoolyear | 102-2 | |
| dc.description.degree | 博士 | |
| dc.contributor.oralexamcommittee | 陳志銘(C. M. Chen),顏怡文(Y. W. Yen),吳子嘉(Albert T. Wu),林士剛(S. K. Lin) | |
| dc.subject.keyword | 三維立體構裝,介金屬反應,顯微結構,體積收縮,孔洞形成, | zh_TW |
| dc.subject.keyword | 3D IC,interfacial reaction,microstructure,volume shrinkage,voids formation, | en |
| dc.relation.page | 77 | |
| dc.rights.note | 有償授權 | |
| dc.date.accepted | 2014-07-21 | |
| dc.contributor.author-college | 工學院 | zh_TW |
| dc.contributor.author-dept | 材料科學與工程學研究所 | zh_TW |
| 顯示於系所單位： | 材料科學與工程學系 | |
文件中的檔案：
| 檔案 | 大小 | 格式 | |
|---|---|---|---|
| ntu-103-1.pdf 未授權公開取用 | 3.11 MB | Adobe PDF |
系統中的文件，除了特別指名其著作權條款之外，均受到著作權保護，並且保留所有的權利。