使用多重臨界電壓互補式金氧半導體技術最佳化設計低電壓、低功率單晶片系統微處理器電路

Abstract

在本論文中，將探討使用多重臨界電壓互補式金氧半導體(MTCMOS)技術設計低電壓低功耗微處理器的效能。第一章介紹了現今電晶體發展的趨勢以及為什麼要設計低功耗的電路。 接著第二章，我們提出了使用多重臨界電壓互補式金氧半導體(MTCMOS)功率消耗最佳化方法(PCOM)設計的32位元單一時脈週期MIPS微處理器功率節省效能的探討，其中，製程是使用90nm互補式金氧半導體(CMOS)技術，操作電壓為1V，全部的電晶體共80,000個。在0.9ns的時脈週期限制下，未使用功率消耗最佳化方法(PCOM)設計，靜態功率(static power)、平均總功率(average total power)和峰值功率(peak power)分別省了27.2%、11.4%和12.5%，而置換的高臨界電壓邏輯單元(HVT logic cell)佔全部邏輯單元的30.3%。 第三章探討使用低功耗設計技術(LPDT)設計的五級管線化(pipelined)MIPS中央處理器的功率消耗表現，製程是使用90nm互補式金氧半導體(CMOS)技術，操作電壓為1V，全部的電晶體共220,000個。根據模擬結果，在時脈週期限制為1.3ns時，使用低功耗設計技術(LPDT)設計的管線化(pipelined)MIPS中央處理器相比沒有優化，在靜態功率(static power)可以節省40.1%、平均總功率(average total power)節省17.8%、峰值功率(peak power)省13.3%。 最後第四章則是本論文的總結和未來可能的延伸研究方向。 顯著的靜態功率(static power)節省或許可以改善現今的手持IT裝置的功率消耗，因為靜態功率(static power)是電池週期很重要的關鍵。

This paper presents a power consumption optimization methodology (PCOM) and a low-power design technique (LPDT) for low-power/ low-voltage microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques. In Chapter 1, the introduction of the CMOS SoC trends is described, followed by the multi-threshold CMOS (MTCMOS) techniques and the digital circuit design flow. In Chapter 2, a power consumption optimization methodology (PCOM) for low-power/ low-voltage single-cycle microprocessor circuit design via multi-threshold CMOS (MTCMOS) techniques has been presented. Based on the optimization methodology with the dual-threshold techniques, a 32-bit single cycle MIPS microprocessor design has been optimized in terms of circuit design using dual-threshold HVT/SVT CMOS devices. According to SPICE simulation results, the power consumption of the 80,000-transistor 32-bit MIPS microprocessor, using a 90nm CMOS technology and operating at 1V with a 0.9-ns clock period, based on the optimization methodology with the dual- threshold technique, has been reduced by 27.23% during the standby period and 12.53% during the dynamic switching period as compared to the one using the conventional standard- threshold SVT CMOS devices. In Chapter 3, a low-power design technique (LPDT) for a low-voltage pipelined microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques has been presented. Using the MTCMOS LPDT, a pipelined MIPS microprocessor circuit having 220,000 transistors with 5 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high threshold-HVT logic cells. According to SPICE simulation results, during the 4-instruction compare operation, this pipelined CPU with the MTCMOS LPDT optimization, designed using a 90nm CMOS technology, operating at 1V and at a 1.3-ns clock period, has been reduced by 40.1% on the leakage power, 17.8% on the average total power and 13.3% on the peak power, as compared to the one using the conventional SVT one. The substantial saving in leakage power consumption for the pipelined CPU with the MTCMOS LPDT optimization could benefit for hand-held IT applications, where leakage power consumption is the key to battery life.