請用此 Handle URI 來引用此文件:
http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57180
標題: | 應用於無線通訊之瓦等級變壓器功率結合式CMOS功率放大器之研製 Research of Watt-Level Transformer Combined CMOS Power Amplifier for Wireless Communication Applications |
作者: | Ian Tseng 曾奕恩 |
指導教授: | 黃天偉(Tian-Wei Huang) |
關鍵字: | 功率放大器,變壓器結合,高輸出功率,高電壓操作,電晶體堆疊, power amplifier,transformer combining,high power,high operating voltage,stacked transistor, |
出版年 : | 2014 |
學位: | 碩士 |
摘要: | 隨著無線通訊系統的發展以及半導體製程的演進,以互補式金氧半場效電晶體實現射頻電路逐漸成為市場焦點,其中功率放大器是收發機中最關鍵的電路,本論文將著重於互補式金氧半場效電晶體功率放大器之設計與分析。
在第三章中,以180奈米互補式金氧半場效電晶體製程實現一個具三維結構之5.3-GHz瓦等級變壓器功率結合式功率放大器。為了降低晶片面積,功率放大器的功率核心使用變壓器以同時達成功率結合、阻抗匹配以及單端與差動訊號的轉換。為了達到近瓦等級的輸出功率,採用放射狀功率分配器及放射狀功率合成器將四路功率核心的功率結合輸出,而放射狀功率結合器同時具有阻抗轉換的功能以降低輸出端匹配網路的阻抗轉換比。藉由將放射狀功率分配器及合成器在電路的中央以三維結構垂直共用同一區域,大幅減小功率分配器以及功率合成器的占用面積,並以一接地屏蔽金屬在重疊的區域做信號隔離,提高放射狀網路的隔離度以及整體電路的穩定度。 在第四章中,以180奈米互補式金氧半場效電晶體製程實現一個5.3-GHz的電晶體堆疊式功率放大器。藉由公式推導以及實際模擬,得到適當的閘極外接電容值,此電容所造成的電壓擺幅將可使所有堆疊電晶體同步操作在相同的電壓擺幅之下,因此輸出電壓擺幅可藉由提高供應電壓來增加,且不會犧牲電路可靠度以及高頻特性。 With the evolution of semiconductor process and development of wireless communication system, implementing radio frequency integrated circuit with CMOS become the focus point of industry market. In the transceiver design, power amplifier is the key and the most critical component. As mentioned above, the design and analysis of CMOS power amplifier is the topic of this thesis. In chapter 3, a 5.3-GHz watt-level transformer combined power amplifier with 3-D architecture implemented in 180-nm CMOS process. In order to reduce the chip size, the power cells of power amplifier use transformer to do power combining, impedance matching and single-to-different ended simultaneously. For watt-level output power design, 4-ways power combining is realized by radial power combiner and power splitter to combine 4 power cells, and the radial power combiner with the function of impedance transformation can also reduce the impedance transform ratio of output matching network. By sharing the same area in 3-D architecture, the occupied area of radial power combiner and power splitter can be minimized significantly. The overlap region of power combiner and splitter will provide a feed-back path which may cause circuit unstable, so the ground shield metal is placed between combiner and splitter to improve the isolation and the amplifier stability. In chapter 4, a 5.3-GHz stacked-FET power amplifier implemented in 180-nm CMOS process. By formula derivation and actual simulation, the proper external capacitance can be found and it allow some gate voltage swing on transistors which can synchronize all stacked device with same operation condition. Thus, the output voltage swing can be increased by rising supply voltage without sacrifice reliability and RF performance. |
URI: | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/57180 |
全文授權: | 有償授權 |
顯示於系所單位: | 電信工程學研究所 |
文件中的檔案:
檔案 | 大小 | 格式 | |
---|---|---|---|
ntu-103-1.pdf 目前未授權公開取用 | 9.33 MB | Adobe PDF |
系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。