三維積體電路矽穿孔結構之信號完整性及隔離區模型建立

Abstract

半導體工業根據摩爾定律，將元件持續進行微縮，以達到更高的效能和更小的面積。但在未來十年，製程技術將面臨瓶頸，且傳統的矽金氧半電晶體的微縮將達到其極限，為了維持摩爾定律，解決方法除了改變電晶體的結構，例如以三維結構的鰭式場效應電晶體或環繞式閘極電晶體取代平面式電晶體，另一個有效方案就是三維積體電路。其中，直通矽穿孔為晶片三維堆疊之重要技術，透過晶片的垂直互連，使得導線路徑更短、傳輸速度更快、消耗功率更低，進一步提高系統的整合度與效能，也降低了晶片的面積，此即為三維積體電路的基礎概念。本篇論文的主軸為模擬矽穿孔在傳遞信號時之插入損耗與雜訊耦合，以及此結構所造成之熱應力對周圍元件電流的影響，並提出矽穿孔周圍元件隔離區的模型。首先，本論文提出一個新的方法，結合高頻電磁效應，如電感和集膚效應，於半導體模擬軟體中，因此可以更正確地計算出傳遞信號在各頻率下的損耗及耦合，並與高頻結構模擬軟體作比較，結果是一致的。第二，由於矽穿孔填充的銅和矽基板熱膨脹係數的差異，會對矽基板產生拉伸和壓縮的應變，可能造成元件電流不當的變化，甚至破壞元件。本論文利用數學模型，加上有限元素模擬軟體分析其熱應力之分布，進一步推導隔離區的模型，可以做為電路設計之準則。最後，額外考慮覆晶封裝中的焊接金屬凸塊對於動態隨機存取記憶體，以及背對面的晶片接合所產生之熱應力，更完整的分析和探討矽穿孔技術可能會遭遇到的問題。

The semiconductor industry has followed the scaling rules according to Moore’s Law. Transistor dimensions have been scaled by 30% every technology generation in order to develop smaller and faster integrated circuits. However, the semiconductor manufacturing technology will meet a bottleneck in 10 years, and the conventional Si MOSFETs will reach scaling limits. Several available solutions are proposed for the continuation of Moore’s Law, such as replacing planar MOSFETs by FinFETs and GAA-FETs. Another promising option is 3D ICs. Through silicon via (TSV) technology is very important and high performance in 3D ICs and 3D packages. The basic concept of 3D ICs is the vertical electrical connection passing through a wafer or die by using TSVs. The electrical paths can be enormously shortened, and the chip area can also be saved by stacking silicon wafers and/or dies. Moreover, it provides heterogeneous integration of different circuit layers, which is more efficient than traditional ICs. This thesis focuses on the insertion loss, noise coupling and thermal stress of TSV structures. In the first part, we proposed a new method to incorporate electromagnetic effects like inductances and the skin effect into TCAD simulation, and the results are consistent with that of the electromagnetic simulation tool: HFSS. When signals propagate along TSVs, the signal integrity is affected by the depletion region and oxide charges. These realistic conditions are involved in our modified TCAD simulation, so a more accurate simulation result of the insertion loss and noise coupling can be achieved. We also investigated the TSV-induced stress, which is due to the different thermal expansion coefficient between the copper pillar and silicon substrate after annealing. It results in a significant carrier mobility variation in the devices. We derived a comprehensive keep-out zone model which defines a forbidden area for devices in order to prevent large current variations. The stress distributions in a Wide I/O TSV array, and the thermal stresses induced by micro-bumps were also investigated. Thus, we give a thoroughly study and analysis on TSV technology in this thesis.