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完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.advisor | 張耀文(Yao-Wen Chang) | |
dc.contributor.author | Iou-Jen Liu | en |
dc.contributor.author | 劉又仁 | zh_TW |
dc.date.accessioned | 2021-06-16T05:29:18Z | - |
dc.date.available | 2016-08-21 | |
dc.date.copyright | 2014-08-21 | |
dc.date.issued | 2014 | |
dc.date.submitted | 2014-08-14 | |
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Liebmann, 'The escalating design impact of resolution-challenged,' Keynote speech in 2013 IEEE/ACM International Conference on Computer-Aided Design. [11] Y.-H. Lin and Y.-L. Li, 'Double patterning lithography aware gridless detailed routing with innovative conflict graph,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 398-403, 2010. [12] G. Luk-Pat, A. Miloslavskya, and B. Painter, 'Design compliance for spacer is dielectric (sid) patterning,' in Proceedings of SPIE, vol. 8326, p. 83260D, 2012. [13] Y. Ma, J. Sweis, C. Bencher, Y. Deng, H. Dai, H. Yoshida, B. Gisuthan, J. Kye, and H. J. Levinson, 'Double patterning compliant logic design,' in Proceedings of SPIE, vol. 7949, p. 79490D, 2011. [14] Y. Ma, J. Sweis, H. Yoshida, Y.Wang, J. Kye, and H. J. Levinson, 'Self-aligned double patterning (sadp) compliant design flow,' in Proceedings of SPIE, vol.8327, p. 832706, 2012. [15] M. Mirsaeedi, J. A. Torres, and M. Anis, 'Self-aligned double-patterning (sadp) friendly detailed routing,' in Proceedings of SPIE, vol. 7974, p. 79740O, 2011. [16] F. Nakajima, C. Kodama, H. Ichikawab, K. Nakayamaa, S. Nojimaa, T. Kotania, S. Mimotogia, and S. Miyamotoa, 'Detailed routing with advanced flexibility and in compliance with self-aligned double patterning constraints,' in Proceedings of SPIE, vol. 8684, p. 86840A, 2013. [17] K. Oyama, E. Nishimura, M. Kushibiki, K. Hasebe, S. Nakajima, H. Murakami, A. H. amd S. Yamauchi, S. Natori, K. Yabe, T. Yamaji, R. Nakatsuji, and H. Yaegashi, 'The important challenge to extend spacer dp process towards 22nm and beyond,' in Proceedings of SPIE, vol. 7639, p. 763907, 2010. [18] V. Wiaux, S. Verhaegen, S. Cheng, F. Iwamoto, P. Jaenen, M. Maenhoudt, T. Matsuda, S. Postnikov, and G. Vandenberghe, 'Split and design guidelines for double patterning,' in Proceedings of SPIE, vol. 6924, p. 692409, 2008. [19] A. K.-K. Wong, Resolution Enhancement Techniques in Optical Lithography. SPIE Publications, 2001. [20] Z. Xiao, Y. Du, H. Tian, and M. D. F.Wong, 'Optimally minimizing overlay violation in self-aligned double patterning decomposition for row-based standard cell layout in polynomial time,' in Proceedings of IEEE/ACM International Conference on Computer-Aided Design, pp.32-39, 2013. [21] Z. Xiao, Y. Du, H. Zhang, and M. D. F. Wong, 'A polynomial time exact algorithm for overlay-resistant self-aligned double patterning (sadp) layout decomposition,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, no. 8, pp. 1228{1239, August 2013. [22] H. Yaegashi, K. Oyama, K. Yabe, S. Yamauchi, A. Hara, and S. Natori, 'Novel approaches to implement the self-aligned spacer double-patterning process toward 11-nm node and beyond,' in Proceedings of SPIE, vol. 7972, p. 79720B, 2011. [23] K. Yuan, J.-S. Yang, and D. Z. Pan, 'Double patterning layout decomposition for simultaneous conflict and stitch minimization,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 2, pp. 185-196, February 2010. [24] H. Zhang, Y. Du, M. D. F. Wong, and R. Topaloglu, 'Self-aligned double patterning decomposition for overlay minimization and hot spot detection,' in Proceedings of ACM/IEEE Design Automation Conference, pp. 71-76, 2011. | |
dc.identifier.uri | http://tdr.lib.ntu.edu.tw/jspui/handle/123456789/56452 | - |
dc.description.abstract | 自對準雙圖案微影技術被認為是最有希望突破傳統光學微影解析
度極限的技術之一。自對準雙圖案微影技術搭配切除光罩近來備受矚 目,因其能提供較高的設計靈活度,例如:自對準雙圖案微影技術搭配 切除光罩能夠不使用縫合圖案而分解奇圈。本論文題出了第一個在細 部繞線時使用切除光罩分解奇圈的演算法。此外,疊對誤差控制亦是 增進良率的關鍵,然而現有的細部繞線演算法皆僅能處理部分的疊對 誤差情形。在本論文中,我們辨別出所有可能造成疊對誤差的電路圖 案,並提出一全新的限制圖來捕捉電路布局中的所有疊對誤差。有了 上述技術,我們的繞線演算法可取得高品質的繞線結果並大幅減少疊 對誤差 (因此提高良率)。 相較於現存的三個最先進的自對準雙圖案微 影繞線演算法,我們提出的演算法能在最短的時間內得到最少的疊對 誤差和完全沒有切除圖案衝突的結果。 | zh_TW |
dc.description.abstract | Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This thesis presents the fi rst work that applies the cut process for decomposing odd cycles during routing.
For SADP, further, overlay control is a critical issue for yield improvement; while published routers can handle only partial overlay scenarios, our work identifies all the scenarios that induce overlays and proposes a novel constraint graph to model all overlays. With the developed techniques, our router can achieve high-quality routing results with significantly fewer overlays (and thus better yields). Compared with three state-of-the-art studies, our algorithm can achieve the best quality and efficiency, with zero cut conflicts, smallest overlay length, highest routability, and fastest running time. | en |
dc.description.provenance | Made available in DSpace on 2021-06-16T05:29:18Z (GMT). No. of bitstreams: 1 ntu-103-R01943144-1.pdf: 1732737 bytes, checksum: 6b2b3ce2961c22fb767ac93c2b657ce3 (MD5) Previous issue date: 2014 | en |
dc.description.tableofcontents | Acknowledgements ii
Abstract (Chinese) iii Abstract v List of Tables viii List of Figures ix Chapter 1. Introduction 1 1.1 Double Patterning Lithography . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.1 Litho-etch-litho-etch Double patterning . . . . . . . . . . . . . . . 2 1.1.2 Self-aligned Double Patterning . . . . . . . . . . . . . . . . . . . . 4 1.2 Related Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2.1 SADP-aware Detailed Routing for the Trim Process . . . . . . . . 9 1.2.2 SADP-aware Detailed Routing for the Cut Process . . . . . . . . . 10 1.3 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Our Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.5 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Chapter 2. Preliminaries 15 2.1 Side Overlay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.2 Design Rules and Cut-Mask Con ict . . . . . . . . . . . . . . . . . . . . 15 2.3 Problem Formulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Chapter 3. Overlay-aware Detailed Routing for SADP Using the Cut Process 18 3.1 Potential Overlay Scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.2 Overlay Constraint Graph . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.3 Linear-Time Color Flipping Algorithm . . . . . . . . . . . . . . . . . . . 35 3.4 Overall Routing Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Chapter 4. Experimental Results 44 4.1 Comparison of SADP-aware routers . . . . . . . . . . . . . . . . . . . . . 44 4.2 Comparison of Rectilinear Polygon Fragmenting Methods . . . . . . . . 48 Chapter 5. Conclusions and Future Work 52 Bibliography 55 Publication List 59 | |
dc.language.iso | en | |
dc.title | 考慮自對準雙圖案微影技術疊對誤差之細部繞線 | zh_TW |
dc.title | Overlay-Aware Detailed Routing for Self-Aligned Double
Patterning Lithography Using the Cut Process | en |
dc.type | Thesis | |
dc.date.schoolyear | 102-2 | |
dc.description.degree | 碩士 | |
dc.contributor.oralexamcommittee | 郭斯彥(Sy-Yen Kuo),張世杰(Shih-Chieh Chang),王廷基(Ting-Chi Wang),李毅郎(Yih-Lang Li) | |
dc.subject.keyword | 實體設計,製造可行性設計,多重圖案微影,自對準雙圖案微影,細部繞線, | zh_TW |
dc.subject.keyword | Physical Design,Design for Manufacturability,Multiple Pat- terning,Self-aligned Double Patterning,Detailed Routing, | en |
dc.relation.page | 59 | |
dc.rights.note | 有償授權 | |
dc.date.accepted | 2014-08-14 | |
dc.contributor.author-college | 電機資訊學院 | zh_TW |
dc.contributor.author-dept | 電子工程學研究所 | zh_TW |
顯示於系所單位: | 電子工程學研究所 |
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